Fabrication of self-assembled nanowire-type interconnects on a semiconductor device

Abstract

Consistent with an example embodiment, there is a semiconductor device with nanowire-type interconnect elements. The semiconductor device comprises a semiconductor substrate with a pn junction formed by a first doped substrate region of a first conductivity type, and a second doped substrate region of an opposite second conductivity type. There is a layer structure on the semiconductor substrate, the layer structure includes a first metal structure which is conductively connected with the first doped substrate region, and further comprising a second metal structure, which is conductively connected with the second doped substrate region. The layer structure allows the transmission of photons with an energy suitable for creating free charge carriers in the first and second doped substrate regions. A third metal structure comprising at least one self-assembled metal dendrite forms an interconnect element between the first and second metal structures.

1 . A semiconductor device, comprising
 a semiconductor substrate with a pn junction formed by a first doped substrate region of a first conductivity type, and a second doped substrate region of an opposite second conductivity type;   a layer structure on the semiconductor substrate, the layer structure comprising the first metal structure, which is conductively connected with the first doped substrate region, and further comprising the second metal structure, which is conductively connected with the second doped substrate region, the layer structure allowing transmission of photons with an energy suitable for creating free charge carriers in the first and second doped substrate regions; and   a third metal structure comprising at least one self-assembled metal dendrite and forming an interconnect element between the first and second metal structures.   
     
     
         2 . The semiconductor device of  claim 1 , wherein the layer structure forms an interconnect stack comprising a plurality of interconnect levels, and the first or second metal structure forms a via between adjacent interconnect levels in the interconnect stack. 
     
     
         3 . The semiconductor device of  claim 1 , wherein the pn junction is formed by doped silicon regions. 
     
     
         4 . The semiconductor device of  claim 1 , wherein the third metal structure and at least one of the first and the second metal structures comprise Cu. 
     
     
         5 . The semiconductor device of  claim 1 , wherein at least one of the first and second doped substrate regions forms a dummy substrate region, which does not have a function during operation of the semiconductor device. 
     
     
         6 . The semiconductor device of  claim 5 , wherein the semiconductor substrate comprises at least one dummy pn junction that does not have a function during operation of the semiconductor device and at least one pn junction that does have a function during operation of the semiconductor device, and wherein respective first and second metal structures connected with respective first and second substrate regions of a respective pn junction are arranged along a trace of the third metal structure on the layer structure so as to form connections to the substrate regions according to an alternating sequence of the type pnpn etc. or npnp etc. 
     
     
         7 - 18 . (canceled)