Programming memory cells with additional data for increased threshold voltage resolution

Abstract

Methods for programming memory and memory devices are provided. According to at least one such method, additional data is appended to original data and the resulting data is programmed in a selected memory cell. The appended data increases the program threshold voltage margin of the original data. The appended data can be a duplicate of the original data or logical zeros. When the selected memory cell is read, the memory control circuitry can read just the original data in the MSB field or the memory control circuitry can read the entire programmed data and ignore the LSB field, for example.

1 . A method for programming memory, the method comprising:
 appending additional data to original data to form a new programming word,
 wherein the additional data are duplicate data of the original data; and programming the memory with the new programming word. 
   
     
     
         2 . The method of  claim 1  and further comprising memory control circuitry controlling transfer of the original data to the memory for programming. 
     
     
         3 . The method of  claim 1  wherein the original data comprises a logical bit. 
     
     
         4 . The method of  claim 1  wherein the original data comprise a plurality of logical bits. 
     
     
         5 . The method of  claim 2  wherein the original data are MSB data bits and the additional data are LSB data bits. 
     
     
         6 . The method of  claim 1  and further comprising transferring one logical bit to the memory and programming further comprises programming three or more logical bits. 
     
     
         7 . The method of  claim 1  and further comprising transferring two logical bits to the memory and programming further comprises programming more than two logical bits. 
     
     
         8 . The method of  claim 1  wherein programming further comprises:
 applying a programming pulse followed by a verify pulse to the memory. 
 
     
     
         9 . A method for programming a memory device, the method comprising:
 transferring at least a portion of original data to memory;   appending additional data to the at least the portion of original data to form a new programming word wherein the additional data are duplicate data of the original data; and   programming the memory in accordance with the new programming word.   
     
     
         10 . The method of  claim 9  wherein transferring the original data comprises memory control circuitry controlling transfer of the at least the portion of original data to the memory array. 
     
     
         11 . The method of  claim 9  and further comprising:
 transferring a remaining portion of the original data, that has not yet been programmed, to the memory; and 
 programming the remaining portion of the original data to the memory. 
 
     
     
         12 . A memory device comprising:
 memory control circuitry configured to control operation of the memory device, the memory control circuitry configured to transfer original data; and   a memory array coupled to the memory control circuitry and configured to receive the original data, the memory array further configured to append additional data to the original data to form a new word, wherein the additional data are duplicate data of the original data, the memory array further configured to be programmed with the new word.   
     
     
         13 . The memory device of  claim 12  wherein the additional data are place holder bits. 
     
     
         14 . The memory device of  claim 12  wherein each memory cell of the memory array is configured to be programmed as a multilevel cell. 
     
     
         15 . The memory device of  claim 12  wherein the memory control circuitry is configured to ignore the appended additional data during a read operation. 
     
     
         16 . The memory device of  claim 12  and further comprising a digital-to-analog converter configured to convert digital bit patterns to threshold voltages to be programmed to the memory array. 
     
     
         17 . The memory device of  claim 12  wherein the memory array is configured to output a signal corresponding to one of four digital bit reference fixed bit patterns for each memory cell that is read. 
     
     
         18 . The memory device of  claim 12  wherein each memory cell of the memory array is configured to be programmed to a voltage indicative of the new word. 
     
     
         19 . The memory device of  claim 12  wherein the memory control circuitry is configured to read only most significant bits of the programmed new word during a read operation.