Semiconductor device having different fin widths

Abstract

A semiconductor device includes at least one source region and at least one drain region. A plurality of fins extend between a source region and a drain region, wherein at least one fin has a different width than another fin. At least one gate is provided to control current flow through such fins. Fin spacing may be varied in addition to, or alternative to utilizing different fin widths.

1 . A transistor comprising:
 a source region;   a drain region;   a first fin extending between the source region and the drain region, wherein the first fin has a first fin width coupled in series with a second fin width, the second fin width different from the first fin width; and   a gate configured to control current flow through the first fin.   
     
     
         2 . The transistor of  claim 1  wherein the transistor includes a p-type transistor. 
     
     
         3 . The transistor of  claim 1 , wherein the transistor includes an n-type transistor 
     
     
         4 . The transistor of  claim 1  wherein the series coupled fin widths include a curved shape. 
     
     
         5 . The transistor of  claim 1  wherein the series coupled fin widths include a tapered shape. 
     
     
         6 . The transistor of  claim 1 , wherein the gate overlaps the first fin width and the second fin width. 
     
     
         7 . The transistor of  claim 1 , wherein the gate overlaps the first fin width and the second fin width asymmetrically. 
     
     
         8 . The transistor of  claim 1 , including a pair of gate contacts disposed on opposite sides of the first fin. 
     
     
         9 . The transistor of  claim 1  including a second fin connected in parallel with the first fin between the source region and the drain region, and wherein the gate is configured to control current flow through the second fin 
     
     
         10 . The transistor of  claim 1 , including a gate contact, wherein at least one gate length and at least one fin width increases as a function of distance from the gate contact. 
     
     
         11 . The transistor of  claim 10 , wherein the second fin includes a third fin width;
 wherein the third fin width is different from the first fin width; and   wherein the third fin width is different from the second fin width.   
     
     
         12 . The transistor of  claim 1 , wherein the gate includes a split gate, the split gate including:
 a first segment disposed over a first fin width;   a second segment disposed over a second fin width;   and an opening, defined by the first segment and the second segment, disposed over an area of the fin where fin edges corresponding to the first fin width meet fin edges corresponding to the second fin width.   
     
     
         13 . The transistor of  claim 12 , wherein the opening is disposed asymmetrically over the area where the fin edges corresponding to the first fin width meet the fin edges corresponding to the second fin width. 
     
     
         14 . The transistor of  claim 1 , wherein the first fin width is positioned under the gate, a portion of the second fin width is positioned under the gate, a portion of a third fin width is positioned under the gate, and the second fin and the third fin width are less than the first fin width to reduce flicker noise. 
     
     
         15 . The transistor of  claim 14 , wherein the second fin width is substantially equal to the third fin width. 
     
     
         16 . The transistor of  claim 14 , wherein the second fin width is greater than the third fin width. 
     
     
         17 . The transistor of  claim 14 , wherein the gate is configured to overlie substantially equal portions of the second fin width and the third fin width. 
     
     
         18 . The transistor of  claim 14 , wherein the gate is configured to asymmetrically overlie the portions of the second and third fin widths. 
     
     
         19 . The transistor of  claim 1 , wherein the first fin width is positioned under the gate, a portion of the second fin width is positioned under the gate, a portion of a third fin width is positioned under the gate, and the second fin and the third fin width are greater than the first fin width to reduce flicker noise. 
     
     
         20 . The transistor of  claim 19 , wherein the gate is configured to asymmetrically overlie the portions of the second and third fin widths.