Hydrogen passivation of integrated circuits

Abstract

An integrated circuit with a passivation trapping layer. An integrated circuit with a hydrogen or deuterium releasing layer underlying a passivation trapping layer. Method for forming an integrated circuit having a hydrogen or deuterium releasing layer. Method for forming an integrated circuit having a passivation trapping layer.

1 . A process of forming an integrated circuit, comprising:
 providing a partially processed integrated circuit having a transistor and a PMD layer overlying said transistor;   passivating said partially processed integrated circuit; and   after said passivating step, depositing a passivation trapping layer over said PMD layer.   
     
     
         2 . The process of  claim 1  further comprising:
 forming contacts within said PMD layer before said step of depositing said passivation trapping layer. 
 
     
     
         3 . The process of  claim 1  further comprising:
 forming contacts within said PMD layer after said step of depositing said passivation trapping layer. 
 
     
     
         4 . The process of  claim 3  further comprising:
 depositing a capping layer on said passivation trapping layer before said step of forming contacts. 
 
     
     
         5 . The process of  claim 1  where said passivating step is a HDP process including at least one of hydrogen and deuterium. 
     
     
         6 . The process of  claim 1  where said passivating step is depositing at least one of a hydrogen releasing layer and a deuterium releasing layer. 
     
     
         7 . The process of  claim 6  where said hydrogen releasing layer is a HDP SiNxHy film with more Si—H bonds than N—H bonds. 
     
     
         8 . The process of  claim 6  where said deuterium releasing layer is a HDP SiNxDy film with more Si-D bonds than N-D bonds. 
     
     
         9 . The process of  claim 1  where said passivating step is annealing said integrated circuit in at least one of a hydrogen and a deuterium containing ambient. 
     
     
         10 . The process of  claim 1  where said passivation trapping layer is a film selected from the group consisting of:
 AlO, 
 AlON, 
 SiNx, and 
 SiNxHy. 
 
     
     
         11 . A process of forming an integrated circuit, comprising:
 providing a partially processed integrated circuit that includes a transistor;   passivating said partially processed integrated circuit;   after said passivating step, depositing a passivation trapping layer over said transistor; and   forming a PMD layer over said passivation trapping layer.