US2012153384A1PendingUtilityA1

Semiconductor Power Device Having A Top-side Drain Using A Sinker Trench

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Assignee: GREBS THOMAS EPriority: Aug 3, 2004Filed: Jan 10, 2012Published: Jun 21, 2012
Est. expiryAug 3, 2024(expired)· nominal 20-yr term from priority
H10P 14/40H10W 20/01H10D 64/2523H10D 64/516H10D 62/127H10D 64/256H10D 64/252H10D 62/116H10D 30/668H10D 30/663H10D 30/665
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Claims

Abstract

A semiconductor package device houses a die which comprises a power device, and the die further includes a silicon region over a substrate, a first plurality of trenches extending in the silicon region; a contiguous sinker trench extending along the perimeter of the die so as to completely surround the first plurality of trenches, the sinker trench extending from a top surface of the die through the silicon region, the sinker trench being lined with an insulator only along the sinker trench sidewalls so that a conductive material filling the sinker trench makes electrical contact with the substrate along the bottom of the sinker trench and makes electrical contact with an interconnect layer along the top of the sinker trench; and a plurality of interconnect balls arranged in a grid array, an outer group of the plurality of interconnect balls electrically connecting to the conductive material in the sinker trench.

Claims

exact text as granted — not AI-modified
1 - 36 . (canceled) 
     
     
         37 . A semiconductor package device housing a die which comprises a power device, the die comprising a silicon region over a substrate, the semiconductor package device comprising:
 a first plurality of trenches extending in the silicon region;   a contiguous sinker trench extending along the perimeter of the die so as to completely surround the first plurality of trenches, the contiguous sinker trench extending from a top surface of the die through the silicon region and terminating within the substrate, the contiguous sinker trench being lined with an insulator only along the sinker trench sidewalls so that a conductive material filling the contiguous sinker trench makes electrical contact with the substrate along the bottom of the contiguous sinker trench and makes electrical contact with an interconnect layer along the top of the contiguous sinker trench; and   a plurality of interconnect balls arranged in a grid array, an outer group of the plurality of interconnect balls electrically connecting to the conductive material in the contiguous sinker trench.   
     
     
         38 . The semiconductor power device of  claim 37  wherein the silicon region is an epitaxial layer and the first plurality of trenches are gate trenches, the semiconductor package device further comprising:
 a well region of a second conductivity type in the epitaxial layer; 
 source regions of the first conductivity type in the well region, the source regions flanking the gate trenches; 
 a gate dielectric layer lining at least the sidewalls of each gate trench; and 
 a gate electrode at least partially filling each gate trench, 
 wherein a gate electrode contact layer electrically contacting the gate electrodes, a source contact layer electrically contacting the source regions, and a drain contact layer electrically contacting the substrate are all along one surface of the semiconductor power device. 
 
     
     
         39 . The semiconductor power device of  claim 37  wherein an inner group of plurality of the interconnect balls surrounded by the outer group of the plurality of the interconnect balls electrically contact the source contact layer. 
     
     
         40 . The semiconductor power device of  claim 37  wherein the contiguous sinker trench is wider and extends deeper than the first plurality of trenches.

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