Rectangular capacitors for dynamic random access memory (dram) and dual-pass lithography methods to form the same

Abstract

A rectangular capacitor for dynamic random access memory (DRAM) and a dual-pass lithography method to form the same are described. For example, a capacitor includes a trench disposed in a first dielectric layer disposed above a substrate. A cup-shaped metal plate is disposed along the bottom and sidewalls of the trench. A second dielectric layer is disposed on and conformal with the cup-shaped metal plate. A trench-fill metal plate is disposed on the second dielectric layer. The second dielectric layer isolates the trench-fill metal plate from the cup-shaped metal plate. The capacitor has a rectangular or near-rectangular shape from a top-down perspective.

1 . An embedded metal-insulator-metal (MIM) capacitor for a semiconductor device, the capacitor comprising:
 a trench disposed in a first dielectric layer disposed above a substrate;   a cup-shaped metal plate disposed along the bottom and sidewalls of the trench;   a second dielectric layer disposed on and conformal with the cup-shaped metal plate; and   a trench-fill metal plate disposed on the second dielectric layer, the second dielectric layer isolating the trench-fill metal plate from the cup-shaped metal plate, wherein the capacitor has a rectangular or near-rectangular shape from a top-down perspective.   
     
     
         2 . The capacitor of  claim 1 , wherein, from the top-down perspective, the capacitor has the near-rectangular shape with slightly rounded corners. 
     
     
         3 . The capacitor of  claim 1 , wherein the sidewalls of the trench comprise a vertical or near-vertical profile. 
     
     
         4 . The capacitor of  claim 1 , wherein the cup-shaped metal plate is electrically coupled to an underlying transistor disposed above the substrate, the transistor included in a dynamic random access memory (DRAM) circuit. 
     
     
         5 . The capacitor of  claim 4 , wherein the cup-shaped metal plate is electrically coupled to the underlying transistor by a floor metal layer disposed below the first dielectric layer. 
     
     
         6 . The capacitor of  claim 1 , wherein the cup-shaped metal plate comprises a copper layer proximate to the bottom of the trench and distal from the second dielectric layer, and comprises a metal nitride layer proximate to the second dielectric layer and distal from the bottom of the trench, and wherein the trench-fill metal plate comprises copper. 
     
     
         7 . The capacitor of  claim 1 , wherein the first dielectric layer is a low-K dielectric layer, and the second dielectric layer is a high-K dielectric layer. 
     
     
         8 .- 13 . (canceled) 
     
     
         14 . An array of embedded metal-insulator-metal (MIM) capacitors for an array of semiconductor devices, the capacitors comprising:
 a plurality of trenches disposed in a first dielectric layer disposed above a substrate;   a plurality of cup-shaped metal plates, each disposed along the bottom and sidewalls of a corresponding trench;   a plurality of second dielectric layers, each disposed on and conformal with a corresponding cup-shaped metal plate; and   a plurality of trench-fill metal plates, each disposed on a corresponding second dielectric layer, the second dielectric layer isolating the corresponding trench-fill metal plate from the corresponding cup-shaped metal plate, wherein the array of capacitors forms a grid pattern, and wherein each of the capacitors has a rectangular or near-rectangular shape from a top-down perspective.   
     
     
         15 . The array of capacitors of  claim 14 , wherein, from the top-down perspective, each capacitor has the near-rectangular shape with slightly rounded corners. 
     
     
         16 . The array of capacitors of  claim 14 , wherein the sidewalls of each trench comprise a vertical or near-vertical profile. 
     
     
         17 . The array of capacitors of  claim 14 , wherein each cup-shaped metal plate is electrically coupled to an underlying transistor disposed above the substrate, the transistor included in a dynamic random access memory (DRAM circuit). 
     
     
         18 . The array of capacitors of  claim 17 , wherein each cup-shaped metal plate is electrically coupled to the underlying transistor by a floor metal layer disposed below the first dielectric layer. 
     
     
         19 . The array of capacitors of  claim 14 , wherein each cup-shaped metal plate comprises a copper layer proximate to the bottom of the corresponding trench and distal from the corresponding second dielectric layer, and comprises a metal nitride layer proximate to the corresponding second dielectric layer and distal from the bottom of the corresponding trench, and wherein each trench-fill metal plate comprises copper. 
     
     
         20 . The array of capacitors of  claim 14 , wherein the first dielectric layer is a low-K dielectric layer, and each second dielectric layer is a high-K dielectric layer.