Inventor · disambiguated record
Nick Lindert
Also filed as: LINDERT NICK
43 granted patents·15 pending applications·2,118 citations·filing 2000–2024
98Inventor score
Top patents by PatentIndex Score
58 records- 0199US7154118B2Bulk non-planar transistor having strained enhanced mobility and methods of fabricationINTEL CORP·Filed 2004·Granted Dec 26, 2006·232 cites·25 claims
- 0298US7332439B2Metal gate transistors with epitaxial source and drain regionsINTEL CORP·Filed 2004·Granted Feb 19, 2008·144 cites·14 claims
- 0398US7326634B2Bulk non-planar transistor having strained enhanced mobility and methods of fabricationINTEL CORP·Filed 2005·Granted Feb 5, 2008·88 cites·18 claims
- 0498US6413802B1Finfet transistor structures having a double gate channel extending vertically from a substrate and methods of manufactureUNIV CALIFORNIA·Filed 2000·Granted Jul 2, 2002·1.2k cites·28 claims
- 0595US7781771B2Bulk non-planar transistor having strained enhanced mobility and methods of fabricationINTEL CORP·Filed 2008·Granted Aug 24, 2010·32 cites·13 claims
- 0695US7060576B2Epitaxially deposited source/drainINTEL CORP·Filed 2003·Granted Jun 13, 2006·72 cites·17 claims
- 0795US6946350B2Controlled faceting of source/drain regionsINTEL CORP·Filed 2003·Granted Sep 20, 2005·98 cites·12 claims
- 0893US7943468B2Penetrating implant for forming a semiconductor deviceINTEL CORP·Filed 2008·Granted May 17, 2011·20 cites·9 claims
- 0993US7314804B2Plasma implantation of impurities in junction region recessesINTEL CORP·Filed 2005·Granted Jan 1, 2008·21 cites·18 claims
- 1092US8519462B26F2 DRAM cellWANG YIH·Filed 2011·Granted Aug 27, 2013·20 cites·11 claims
- 1191US7427775B2Fabricating strained channel epitaxial source/drain transistorsINTEL CORP·Filed 2007·Granted Sep 23, 2008·17 cites·5 claims
- 1288US9691839B2Metal-insulator-metal (MIM) capacitor with insulator stack having a plurality of metal oxide layersLINDERT NICK·Filed 2011·Granted Jun 27, 2017·12 cites·37 claims
- 1387US6787440B2Method for making a semiconductor device having an ultra-thin high-k gate dielectricINTEL CORP·Filed 2002·Granted Sep 7, 2004·41 cites·13 claims
- 1486US10541143B2Self-aligned build-up of topographic featuresINTEL CORP·Filed 2016·Granted Jan 21, 2020·4 cites·20 claims
- 1584US7226842B2Fabricating strained channel epitaxial source/drain transistorsINTEL CORP·Filed 2004·Granted Jun 5, 2007·27 cites·13 claims
- 1683US9972541B2Technique for filling high aspect ratio, narrow structures with multiple metal layers and associated configurationsINTEL CORP·Filed 2014·Granted May 15, 2018·5 cites·20 claims
- 1781US7704833B2Method of forming abrupt source drain metal gate transistorsINTEL CORP·Filed 2004·Granted Apr 27, 2010·22 cites·6 claims
- 1880US10109628B2Transistor device with gate control layer undercutting the gate dielectricINTEL CORP·Filed 2013·Granted Oct 23, 2018·4 cites·8 claims
- 1980US7045073B2Pre-etch implantation damage for the removal of thin film layersINTEL CORP·Filed 2002·Granted May 16, 2006·22 cites·15 claims
- 2079US9076758B2Rectangular capacitors for dynamic random access (DRAM) and dual-pass lithography methods to form the sameLINDERT NICK·Filed 2013·Granted Jul 7, 2015·4 cites·6 claims
- 2178US11217582B2Unidirectional self-aligned gate endcap (SAGE) architectures with gate-orthogonal wallsINTEL CORP·Filed 2018·Granted Jan 4, 2022·2 cites·13 claims
- 2278US8502293B2Capacitor with recessed plate portion for dynamic random access memory (DRAM) and method to form the sameLINDERT NICK·Filed 2010·Granted Aug 6, 2013·5 cites·37 claims
- 2377US12426316B2Method of fabricating integrated circuits with fin trim plug structures having an oxidation catalyst layer surrounded by a recessed dielectric materialINTEL CORP·Filed 2022·Granted Sep 23, 2025·0 cites·24 claims
- 2476US8344452B2Metal gate transistors with raised source and drain regions formed on heavily doped substrateINTEL CORP·Filed 2008·Granted Jan 1, 2013·4 cites·8 claims
- 2574US8030197B2Recessed channel array transistor (RCAT) in replacement metal gate (RMG) logic flowINTEL CORP·Filed 2009·Granted Oct 4, 2011·4 cites·20 claims
- 2674US7981756B2Common plate capacitor array connections, and processes of making sameINTEL CORP·Filed 2008·Granted Jul 19, 2011·5 cites·22 claims
- 2772US8441097B2Methods to form memory devices having a capacitor with a recessed electrodeSTEIGERWALD JOSEPH M·Filed 2009·Granted May 14, 2013·5 cites·12 claims
- 2870US9224794B2Embedded memory device having MIM capacitor formed in excavated structureINTEL CORP·Filed 2013·Granted Dec 29, 2015·1 cites·6 claims
- 2968US9565766B2Formation of DRAM capacitor among metal interconnectLINDERT NICK·Filed 2011·Granted Feb 7, 2017·2 cites·31 claims
- 3067US9577030B2Semiconductor structure having a capacitor and metal wiring integrated in a same dielectric layerLINDERT NICK·Filed 2015·Granted Feb 21, 2017·1 cites·6 claims
- 3167US6936518B2Creating shallow junction transistorsINTEL CORP·Filed 2004·Granted Aug 30, 2005·8 cites·14 claims
- 3266US7927959B2Method of patterning a metal on a vertical sidewall of an excavated feature, method of forming an embedded MIM capacitor using same, and embedded memory device produced therebyINTEL CORP·Filed 2008·Granted Apr 19, 2011·3 cites·15 claims
- 3365US11688792B2Dual self-aligned gate endcap (SAGE) architecturesINTEL CORP·Filed 2021·Granted Jun 27, 2023·0 cites·25 claims
- 3464US11605632B2Unidirectional self-aligned gate endcap (SAGE) architectures with gate-orthogonal wallsINTEL CORP·Filed 2021·Granted Mar 14, 2023·0 cites·20 claims
- 3563US8441057B2Embedded memory device having MIM capacitor formed in excavated structureKEATING STEVEN J·Filed 2011·Granted May 14, 2013·1 cites·7 claims
- 3662US8426927B2Penetrating implant for forming a semiconductor deviceCURELLO GIUSEPPE·Filed 2011·Granted Apr 23, 2013·1 cites·4 claims
- 3762US7951673B2Forming abrupt source drain metal gate transistorsINTEL CORP·Filed 2010·Granted May 31, 2011·1 cites·6 claims
- 3859US11538937B2Fin trim plug structures having an oxidation catalyst layer surrounded by a recessed dielectric materialINTEL CORP·Filed 2019·Granted Dec 27, 2022·0 cites·21 claims
- 3958US2025374619A1Gated subfin reduction techniques in nanoribbon-based transistorsINTEL CORP·Filed 2024·Application pending·0 cites
- 4055US6808993B2Ultra-thin gate dielectricsINTEL CORP·Filed 2003·Granted Oct 26, 2004·8 cites·22 claims
- 4155US2025194223A1Uniaxial dual strain in ribbonized channelINTEL CORP·Filed 2023·Application pending·0 cites
- 4254US11205708B2Dual self-aligned gate endcap (SAGE) architecturesINTEL CORP·Filed 2018·Granted Dec 21, 2021·0 cites·21 claims
- 4354US7671358B2Plasma implantated impurities in junction region recessesINTEL CORP·Filed 2007·Granted Mar 2, 2010·0 cites·24 claims
- 4453US2025194179A1Integrated circuit structures with backside contacts and asymmetric source and drain regionsCHU TAO·Filed 2023·Application pending·0 cites
- 4552US8741720B2Penetrating implant for forming a semiconductor deviceCURELLO GIUSEPPE·Filed 2013·Granted Jun 3, 2014·0 cites·7 claims
- 4651US11562999B2Cost effective precision resistor using blocked DEPOP method in self-aligned gate endcap (SAGE) architectureINTEL CORP·Filed 2018·Granted Jan 24, 2023·0 cites·11 claims
- 4749US2006197164A1Epitaxially deposited source/drainLINDERT NICK·Filed 2006·Application pending·0 cites
- 4848US2017148868A1Formation of dram capacitor among metal interconnectINTEL CORP·Filed 2017·Application pending·0 cites
- 4948US2005191834A1Creating shallow junction transistorsFiled 2005·Application pending·0 cites
- 5047US2012223413A1Semiconductor structure having a capacitor and metal wiring integrated in a same dielectric layerLINDERT NICK·Filed 2011·Application pending·0 cites
Showing the top 50 of 58 patent records by PatentIndex Score.
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →