Formation of dram capacitor among metal interconnect

Abstract

Techniques are disclosed for integrating capacitors among the metal interconnect for embedded DRAM applications. In some embodiments, the technique uses a wet etch to completely remove the interconnect metal (e.g., copper) that is exposed prior to the capacitor formation. This interconnect metal removal precludes that metal from contaminating the hi-k dielectric of the capacitor. Another benefit is increased height (surface area) of the capacitor, which allows for increased charge storage. In one example embodiment, an integrated circuit device is provided that includes a substrate having at least a portion of a DRAM bit cell circuitry, an interconnect layer on the substrate and including one or more metal-containing interconnect features, and a capacitor at least partly in the interconnect layer and occupying space from which a metal-containing interconnect feature was removed. The integrated circuit device can be, for example, a processor or a communications device.

What is claimed is: 
     
         1 . An integrated circuit device, comprising:
 a first layer comprising insulation material defining a first space and a second space, the first space having a cross-sectional scale and a cross-sectional shape, the second space also having the cross-sectional scale and cross-sectional shape;   a metal-containing interconnect feature occupying the first space; and   a capacitor occupying the second space, the capacitor including a bottom electrode, a dielectric, and a top electrode, wherein each of the bottom electrode, dielectric, and top electrode are at least within the second space.   
     
     
         2 . The integrated circuit device of  claim 1 , further comprising a diffusion barrier layer in the second space between at least a portion of the bottom electrode of the capacitor and the first layer, the diffusion barrier layer conformal to at least the second space. 
     
     
         3 . The integrated circuit device of  claim 2 , wherein the diffusion barrier layer comprises tantalum. 
     
     
         4 . The integrated circuit device of  claim 1 , wherein the capacitor comprises a metal-insulator-metal (MIM) capacitor. 
     
     
         5 . The integrated circuit device of  claim 1 , wherein the cross-sectional shape comprises a first width and an adjacent second width less than the first width. 
     
     
         6 . The integrated circuit device of  claim 5 , wherein the metal-containing interconnect feature in the first space comprises:
 a metal line in the first width of the cross-sectional shape; and   a via in the adjacent second width of the cross-sectional shape.   
     
     
         7 . The integrated circuit device of  claim 5 , wherein the cross-sectional shape further comprises a tapered portion having a uniformly decreasing width from a top to a bottom, the bottom of the tapered portion adjacent to the first width of the cross-sectional shape. 
     
     
         8 . The integrated circuit device of  claim 1 , wherein the cross-sectional shape has an aspect ratio of from 5:1 to 10:1. 
     
     
         9 . The integrated circuit device of  claim 1 , wherein the bottom electrode of the capacitor is electrically coupled to a transistor of a random access memory bit cell. 
     
     
         10 . The integrated circuit device of  claim 1 , wherein the integrated circuit device of  claim 1  is one of a processor, a communications device, and a computing device. 
     
     
         11 . A system comprising:
 a processor integrated circuit comprising the integrated circuit device of  claim 1 ; and   at least one of a communications integrated circuit and a display.   
     
     
         12 . An integrated circuit device, comprising:
 a first layer comprising insulation material defining a first space and a second space, the first space having a cross-sectional scale and a cross-sectional shape, the second space also having the cross-sectional scale and cross-sectional shape;   a metal-containing interconnect feature occupying the first space;   a capacitor occupying the second space, the capacitor including a bottom electrode, a dielectric, and a top electrode, wherein each of the bottom electrode, dielectric, and top electrode are at least within the second space; and   a diffusion barrier layer in the second space between at least a portion of the bottom electrode of the capacitor and the first layer, the diffusion barrier layer having the cross-sectional scale and the cross-sectional shape of the second space.   
     
     
         13 . The integrated circuit device of  claim 12 , wherein the cross-sectional shape comprises a first width and an adjacent second width less than the first width. 
     
     
         14 . The integrated circuit device of  claim 13 , wherein the metal-containing interconnect feature in the first space comprises:
 a metal line in the first width of the cross-sectional shape; and   a via in the adjacent second width of the cross-sectional shape.   
     
     
         15 . A system comprising:
 a processor integrated circuit comprising the integrated circuit device of  claim 12 ; and   at least one of a communications integrated circuit and a display.   
     
     
         16 . An integrated circuit device, comprising:
 a first layer comprising insulation material defining a first interconnect pathway and a second interconnect pathway, the first interconnect pathway and the second interconnect pathway having a cross-sectional scale and a cross-sectional shape;   a metal-containing interconnect feature occupying the first interconnect pathway; and   a capacitor occupying the second interconnect pathway, the capacitor including a bottom electrode, a dielectric, and a top electrode, wherein each of the bottom electrode, dielectric, and top electrode are at least within the second interconnect pathway.   
     
     
         17 . The integrated circuit device of  claim 16 , further comprising a diffusion barrier layer in the second interconnect pathway between at least a portion of the bottom electrode of the capacitor and the first layer, the diffusion barrier layer having the cross-sectional scale and the cross-sectional shape of the second interconnect pathway. 
     
     
         18 . The integrated circuit device of  claim 16 , wherein the cross-sectional shape comprises a first width and an adjacent second width less than the first width. 
     
     
         19 . The integrated circuit device of  claim 16 , wherein the bottom electrode of the capacitor is electrically coupled to a transistor of a random access memory bit cell. 
     
     
         20 . A system comprising:
 a processor integrated circuit comprising the integrated circuit device of  claim 16 ; and   at least one of a communications integrated circuit and a display.