US2006197164A1PendingUtilityA1

Epitaxially deposited source/drain

49
Assignee: LINDERT NICKPriority: Oct 24, 2003Filed: Apr 20, 2006Published: Sep 7, 2006
Est. expiryOct 24, 2023(expired)· nominal 20-yr term from priority
H10P 10/00H10D 62/021H10D 30/00H10D 44/45H10D 30/0275
49
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Claims

Abstract

An epitaxially deposited source/drain extension may be formed for a metal oxide semiconductor field effect transistor. A sacrificial layer may be formed and etched away to undercut under the gate electrode. Then a source/drain extension of epitaxial silicon may be deposited to extend under the edges of the gate electrode. As a result, the extent by which the source/drain extension extends under the gate may be controlled by controlling the etching of the sacrificial material. Its thickness and depth may be controlled by controlling the deposition process. Moreover, the characteristics of the source/drain extension may be controlled independently of those of the subsequently formed deep or heavily doped source/drain junction.

Claims

exact text as granted — not AI-modified
1 . A field effect transistor comprising: 
 a substrate;    a doped epitaxial semiconductor material formed over said substrate; and    a gate electrode formed over said doped epitaxial semiconductor material, said doped epitaxial semiconductor material extending under said gate electrode.    
   
   
       2 . The transistor of  claim 1  including a source/drain having a source/drain extension, said source/drain extension being formed of said doped epitaxial semiconductor material and extends under the edges of the gate electrode.  
   
   
       3 . The transistor of  claim 2  wherein said material has a first thickness near said gate electrode and a second thickness spaced from said gate electrode, said second thickness being greater than said first thickness.  
   
   
       4 . The transistor of  claim 3  including a sidewall spacer, said material extending under said sidewall spacer.  
   
   
       5 . The transistor of  claim 4  wherein said second thickness is aligned with said sidewall spacer.  
   
   
       6 . The transistor of  claim 1  wherein said transistor is a delta doped transistor.  
   
   
       7 . The transistor of  claim 1  including an ion implanted source/drain under said doped epitaxial semiconductor material.

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