Semiconductor structure having a capacitor and metal wiring integrated in a same dielectric layer

Abstract

Semiconductor structures having capacitors and metal wiring integrated in a same dielectric layer are described. For example, a semiconductor structure includes a plurality of semiconductor devices disposed in or above a substrate. One or more dielectric layers are disposed above the plurality of semiconductor devices. Metal wiring is disposed in each of the dielectric layers. The metal wiring is electrically coupled to one or more of the semiconductor devices. A metal-insulator-metal (MIM) capacitor is disposed in one of the dielectric layers, adjacent to the metal wiring of the at least one of the dielectric layers. The MIM capacitor is electrically coupled to one or more of the semiconductor devices.

1 . A semiconductor structure, comprising:
 a plurality of semiconductor devices disposed in or above a substrate;   one or more dielectric layers disposed above the plurality of semiconductor devices;   metal wiring disposed in each of the dielectric layers and electrically coupled to one or more of the semiconductor devices; and   a metal-insulator-metal (MIM) capacitor disposed in at least one of the dielectric layers, adjacent to the metal wiring of the at least one of the dielectric layers, and electrically coupled to one or more of the semiconductor devices.   
     
     
         2 . The semiconductor structure of  claim 1 , wherein at least a portion of the metal wiring is electrically coupled to one or more semiconductor devices included in a logic circuit, and wherein the MIM capacitor is an embedded dynamic random access memory (eDRAM) capacitor. 
     
     
         3 . The semiconductor structure of  claim 1 , wherein the MIM capacitor is disposed in only one of the dielectric layers. 
     
     
         4 . The semiconductor structure of  claim 1 , wherein the MIM capacitor is disposed in only two of the dielectric layers, adjacent to the metal wiring of each of the two dielectric layers and also adjacent to a via coupling the metal wiring of each of the two dielectric layers. 
     
     
         5 . The semiconductor structure of  claim 1 , wherein the MIM capacitor is disposed in more than two of the dielectric layers, adjacent to the metal wiring of all of the more than two dielectric layers. 
     
     
         6 . The semiconductor structure of  claim 1 , further comprising:
 one or more etch-stop layers, an etch-stop layer disposed between each of the dielectric layers, and directly below the dielectric layer closest to the substrate.   
     
     
         7 . The semiconductor structure of  claim 1 , wherein the MIM capacitor is disposed in a trench disposed in the at least one of the dielectric layers, and wherein the MIM capacitor comprises:
 a cup-shaped metal plate disposed along the bottom and sidewalls of the trench;   a second dielectric layer disposed on and conformal with the cup-shaped metal plate; and   a trench-fill metal plate disposed on the second dielectric layer, the second dielectric layer isolating the trench-fill metal plate from the cup-shaped metal plate.   
     
     
         8 . The semiconductor structure of  claim 7 , wherein the sidewalls of the trench comprise a vertical or near-vertical profile. 
     
     
         9 . The semiconductor structure of  claim 7 , wherein the sidewalls of the trench taper outward from the bottom of the at least one of the dielectric layers to the top of the at least one of the dielectric layers. 
     
     
         10 . The semiconductor structure of  claim 7 , wherein the at least one of the dielectric layers is a low-K dielectric layer, and the second dielectric layer is a high-K dielectric layer. 
     
     
         11 . A semiconductor structure, comprising:
 a plurality of semiconductor devices disposed in or above a substrate;   a first dielectric layer disposed above the plurality of semiconductor devices and having disposed therein contacts electrically coupled to the plurality of semiconductor devices;   a second dielectric layer disposed above the first dielectric layer and having disposed therein a first metal wiring and one or more vias coupling the first metal wiring to the contacts;   a third dielectric layer disposed above the second dielectric layer and having disposed therein a second metal wiring and one or more vias coupling the second metal wiring to the first metal wiring;   a fourth dielectric layer disposed above the third dielectric layer and having disposed therein a third metal wiring and one or more vias coupling the third metal wiring to the second metal wiring;   a fifth dielectric layer disposed above the fourth dielectric layer and having disposed therein a fourth metal wiring and one or more vias coupling the fourth metal wiring to the third metal wiring, and also having therein at least a portion of a metal-insulator-metal (MIM) capacitor, the MIM capacitor adjacent to the fourth metal wiring and electrically coupled to one or more of the semiconductor devices; and   a sixth dielectric layer disposed above the fifth dielectric layer and having disposed therein a fifth metal wiring and one or more vias coupling the fifth metal wiring to the fourth metal wiring.   
     
     
         12 . The semiconductor structure of  claim 11 , wherein at least a portion of the fourth metal wiring is electrically coupled to one or more semiconductor devices included in a logic circuit, and wherein the MIM capacitor is an embedded dynamic random access memory (eDRAM) capacitor. 
     
     
         13 . The semiconductor structure of  claim 11 , wherein the MIM capacitor is disposed in the fifth dielectric layer, but not the fourth or sixth dielectric layers. 
     
     
         14 . The semiconductor structure of  claim 11 , wherein another portion of the MIM capacitor is disposed in the fourth dielectric layer, adjacent to the third metal wiring, but no portion of the MIM capacitor is disposed in the third or the sixth dielectric layers. 
     
     
         15 . The semiconductor structure of  claim 11 , wherein another portion of the MIM capacitor is disposed in the fourth and sixth dielectric layers, adjacent to the third and fifth metal wirings, but no portion of the MIM capacitor is disposed in the third dielectric layer. 
     
     
         16 . The semiconductor structure of  claim 11 , further comprising:
 a plurality of etch-stop layers, an etch-stop layer disposed between each of the first, second, third, fourth, fifth and sixth dielectric layers.   
     
     
         17 . The semiconductor structure of  claim 11 , wherein the MIM capacitor is disposed in a trench disposed in at least the fifth dielectric layer, and wherein the MIM capacitor comprises:
 a cup-shaped metal plate disposed along the bottom and sidewalls of the trench;   a seventh dielectric layer disposed on and conformal with the cup-shaped metal plate; and   a trench-fill metal plate disposed on the seventh dielectric layer, the seventh dielectric layer isolating the trench-fill metal plate from the cup-shaped metal plate.   
     
     
         18 . The semiconductor structure of  claim 17 , wherein the sidewalls of the trench comprise a vertical or near-vertical profile. 
     
     
         19 . The semiconductor structure of  claim 17 , wherein the sidewalls of the trench taper outward from the bottom to the top of the fifth dielectric layer. 
     
     
         20 . The semiconductor structure of  claim 17 , wherein the second, third, fourth, fifth and sixth dielectric layers are low-K dielectric layers, and the seventh dielectric layer is a high-K dielectric layer. 
     
     
         21 . A method of fabricating a semiconductor structure, the method comprising:
 forming a plurality of semiconductor devices in or above a substrate;   forming one or more dielectric layers above the plurality of semiconductor devices;   forming metal wiring in each of the dielectric layers, the forming comprising electrically coupling the metal wiring to one or more of the semiconductor devices; and   forming a metal-insulator-metal (MIM) capacitor in at least one of the dielectric layers adjacent to the metal wiring of the at least one of the dielectric layers, the forming comprising electrically coupling the MIM capacitor to one or more of the semiconductor devices.   
     
     
         22 . The method of  claim 21 , wherein electrically coupling the metal wiring to one or more of the semiconductor devices comprises coupling to one or more semiconductor devices included in a logic circuit, and wherein forming the MIM capacitor comprises forming an embedded dynamic random access memory (eDRAM) capacitor. 
     
     
         23 . The method of  claim 21 , wherein forming the MIM capacitor comprises forming the MIM capacitor in only one of the dielectric layers. 
     
     
         24 . The method of  claim 21 , wherein forming the MIM capacitor comprises forming the MIM capacitor in only two of the dielectric layers, adjacent to the metal wiring of each of the two dielectric layers and also adjacent to a via coupling the metal wiring of each of the two dielectric layers, the method further comprising:
 subsequent to forming the first of the two of the dielectric layers and prior to forming the second of the two of the dielectric layers and the MIM capacitor, forming an etch-stop layer on the first of the two of the dielectric layers; and   patterning the etch-stop layer to open a region for subsequently forming the MIM capacitor, wherein the second of the two of the dielectric layers is formed on the patterned etch-stop layer and in the region.   
     
     
         25 . The method of  claim 21 , wherein forming the MIM capacitor comprises forming the MIM capacitor in more than two of the dielectric layers, adjacent to the metal wiring of all of the more than two dielectric layers. 
     
     
         26 . The method of  claim 21 , further comprising:
 forming one or more etch-stop layers, including forming an etch-stop layer between each of the dielectric layers, and directly below the dielectric layer closest to the substrate.   
     
     
         27 . The method of  claim 21 , wherein forming the MIM capacitor comprises:
 forming a trench in the at least one of the dielectric layers;   forming a cup-shaped metal plate along the bottom and sidewalls of the trench;   forming a second dielectric layer on and conformal with the cup-shaped metal plate; and   forming a trench-fill metal plate on the second dielectric layer, the second dielectric layer isolating the trench-fill metal plate from the cup-shaped metal plate.   
     
     
         28 . The method of  claim 27 , wherein forming the trench comprises forming the sidewalls of the trench to have a vertical or near-vertical profile. 
     
     
         29 . The method of  claim 27 , wherein forming the trench comprises forming the sidewalls of the trench to taper outward from the bottom of the at least one of the dielectric layers to the top of the at least one of the dielectric layers. 
     
     
         30 . The method of  claim 27 , wherein forming the one or more dielectric layers comprises forming one or more low-K dielectric layers, and forming the second dielectric layer comprises forming a high-K dielectric layer.