Semiconductor Device and Method of Forming Low Voltage MOSFET for Portable Electronic Devices and Data Processing Centers

Abstract

A semiconductor device has a well region formed within a substrate. A gate structure is formed over a surface of the substrate. A source region is formed within the substrate adjacent to the gate structure. A drain region is formed within the substrate adjacent to the gate structure. A first clamping region and second clamping region below the source region and drain region. A trench is formed through the source region. The trench allows the width of the source region to be reduced to 0.94 to 1.19 micrometers. A plug is formed through the trench. A source tie is formed through the trench over the plug. An interconnect structure is formed over the source region, drain region, and gate structure. The semiconductor device can be used in a power supply to provide a low voltage to electronic equipment such as a portable electronic device and data processing center.

1 . A method of making a semiconductor device, comprising:
 providing a substrate;   forming a well region within the substrate;   forming a gate structure over the substrate;   forming a source region within the substrate adjacent to the gate structure;   forming a drain region within the substrate adjacent to the gate structure opposite the source region;   forming a trench through the source region;   forming a plug through the trench within the substrate; and   forming a source tie through the trench over the plug.   
     
     
         2 . The method of  claim 1 , further including forming a clamping region below the drain region or source region. 
     
     
         3 . The method of  claim 1 , further including forming a voltage threshold adjust region over the substrate. 
     
     
         4 . The method of  claim 1 , further including:
 forming an interconnect structure over the source region, drain region, and gate structure; and   forming a salicide layer over the source region, source tie, gate structure, and drain region prior to forming the interconnect structure.   
     
     
         5 . The method of  claim 1 , further including forming an insulating layer adjacent to the gate structure. 
     
     
         6 . The method of  claim 1 , further including forming the trench in a straight, serpentine, sawtooth, or discrete offset sectional configuration. 
     
     
         7 . The method of  claim 1 , wherein the source region has a width less than 1.19 micrometers. 
     
     
         8 . A method of making a semiconductor device, comprising:
 providing a substrate;   forming a well region within the substrate;   forming a gate structure over the substrate;   forming a source region within the substrate adjacent to the gate structure;   forming a drain region within the substrate adjacent to the gate structure opposite the source region;   forming a trench through the source region; and   forming a plug through the trench within the substrate.   
     
     
         9 . The method of  claim 8 , further including forming a source tie through the trench over the plug. 
     
     
         10 . The method of  claim 8 , further including forming a clamping region below the drain region or source region. 
     
     
         11 . The method of  claim 8 , further including forming an insulating layer adjacent to the gate structure. 
     
     
         12 . The method of  claim 8 , further including forming the trench in a straight, serpentine, sawtooth, or discrete offset sectional configuration. 
     
     
         13 . The method of  claim 8 , wherein the source region has a width less than 1.19 micrometers. 
     
     
         14 . A method of making a semiconductor device, comprising:
 providing a substrate;   forming a well region within the substrate;   forming a gate structure over the substrate;   forming a source region within the substrate adjacent to the gate structure;   forming a drain region within the substrate adjacent to the gate structure opposite the source region; and   forming a trench through the source region.   
     
     
         15 . The method of  claim 14 , further including forming a plug through the trench within the substrate. 
     
     
         16 . The method of  claim 15 , further including forming a source tie through the trench over the plug. 
     
     
         17 . The method of  claim 14 , further including forming a clamping region below the drain region or source region. 
     
     
         18 . The method of  claim 14 , further including forming an insulating layer adjacent to the gate structure. 
     
     
         19 . The method of  claim 14 , further including forming the trench in a straight, serpentine, sawtooth, or discrete offset sectional configuration. 
     
     
         20 . The method of  claim 14 , wherein the source region has a width less than 1.19 micrometers. 
     
     
         21 . A semiconductor device, comprising:
 a substrate;   a well region formed within the substrate;   a gate structure formed over the substrate;   a source region formed within the substrate adjacent to the gate structure;   a drain region formed within the substrate adjacent to the gate structure opposite the source region; and   a trench formed through the source region.   
     
     
         22 . The semiconductor device of  claim 21 , further including a plug formed through the trench within the substrate. 
     
     
         23 . The semiconductor device of  claim 22 , further including a source tie formed through the trench over the plug. 
     
     
         24 . The semiconductor device of  claim 21 , further including a clamping region formed below the drain or source region. 
     
     
         25 . The semiconductor device of  claim 21 , further including an insulating layer formed adjacent to the gate structure.