Superjunction semiconductor device

Abstract

A superjunction semiconductor device includes an edge p pillar, an active region, and a termination region. The edge p pillar has a rectangular ring shape with rounded corners. The edge p pillar has an outer region surrounding the active region and an inner region on in the sides of the active region. The active region has active p pillars and active n pillars having vertical stripe shapes. The active p pillars and the active n pillars are alternately arranged horizontally in the active region. The termination region includes termination n pillars and termination p pillars alternately arranged around the edge p pillar.

1 .- 10 . (canceled) 
     
     
         11 . A superjunction semiconductor device comprising:
 an edge p pillar having a first width and a rectangular ring shape with rounded corners;   an active region surrounded by the edge p pillar, the active region having active p pillars having vertical stripe shapes with a second width twice the first width and active n pillars, the active p pillars and the active n pillars being alternately arranged horizontally in the active region; and   a termination region including termination n pillars and termination p pillars alternately arranged around the edge p pillar.   
     
     
         12 . The superjunction semiconductor device of  claim 11 , wherein the distance between the central axis of each side of the edge p pillar and the vertical central axis of the corresponding active p pillar disposed closest to each side of the edge p pillar is equal to half the distance between the vertical central axes of neighboring active p pillars. 
     
     
         13 . The superjunction semiconductor device of  claim 11 , wherein the widths of the upper and lower parts of the active p pillars are gradually decreased or increased toward each end of the upper and lower parts in the corners of the active region. 
     
     
         14 . The superjunction semiconductor device of  claim 13 , wherein the widths of the upper and lower parts of the active p pillars are gradually decreased when the quantity of p charges is larger than the quantity of n charges and gradually increased when the quantity of p charges is smaller than the quantity of n charges. 
     
     
         15 . The superjunction semiconductor device of  claim 11 , further comprising subsidiary p pillars arranged in the active n pillars to compensate for the small quantity of p charges in the active p pillars in the corners of the active region. 
     
     
         16 . The superjunction semiconductor device of  claim 15 , wherein the subsidiary p pillars have bar shapes vertically arranged in the active n pillars in the corners of the active region. 
     
     
         17 . The superjunction semiconductor device of  claim 15 , wherein the subsidiary p pillars are in the form of islands arranged at predetermined intervals in the active n pillars in the corners of the active region. 
     
     
         18 . The superjunction semiconductor device of  claim 15 , wherein the subsidiary p pillars have bent belt shapes arranged along the inner side of and contacting the edge p pillar in the active n pillars in the corners of the active region. 
     
     
         19 . A superjunction semiconductor device comprising:
 an active region having active p pillars and active n pillars having vertical stripe shapes, the active p pillars and the active n pillars being alternately arranged horizontally in the active region;   an edge p pillar having a rectangular ring shape with rounded corners, the edge p pillar including an outer region surrounding the active region and an inner region disposed on the sides of the active region; and   a termination region including termination n pillars and termination p pillars alternately arranged around the edge p pillar.   
     
     
         20 . The superjunction semiconductor device of  claim 19 , wherein the width of the corners, and upper and lower parts of the edge p pillar where only the outer region is arranged is equal to half the width of each of the active p pillars. 
     
     
         21 . The superjunction semiconductor device of  claim 20 , wherein the width of the edge p pillar where both the outer region and the inner region are arranged is identical to the width of each of the active p pillars. 
     
     
         22 . The superjunction semiconductor device of  claim 19 , wherein the distance between the boundary between the outer region and the inner region and the vertical central axis of the active p pillar disposed closest to the edge p pillar is identical to the distance between the vertical central axes of neighboring active p pillars. 
     
     
         23 . The superjunction semiconductor device of  claim 19 , wherein the widths of the upper and lower parts of the active p pillars are gradually decreased or increased toward each end of the upper and lower parts in the corners of the active region. 
     
     
         24 . The superjunction semiconductor device of  claim 23 , wherein the widths of the upper and lower parts of the active p pillars are gradually decreased when the quantity of p charges is larger than the quantity of n charges and gradually increased when the quantity of p charges is smaller than the quantity of n charges. 
     
     
         25 . The superjunction semiconductor device of  claim 19 , further comprising subsidiary p pillars arranged in the active n pillars to compensate for the small quantity of p charges in the active p pillars in the corners of the active region. 
     
     
         26 . The superjunction semiconductor device of  claim 25 , wherein the subsidiary p pillars have bar shapes vertically arranged in the active n pillars in the corners of the active region. 
     
     
         27 . The superjunction semiconductor device of  claim 25 , wherein the subsidiary p pillars are in the form of islands arranged at predetermined intervals in the active n pillars in the corners of the active region. 
     
     
         28 . The superjunction semiconductor device of  claim 25 , wherein the subsidiary p pillars have bent belt shapes arranged along the inner side of and contacting the edge p pillar in the active n pillars in the corners of the active region. 
     
     
         29 . A superjunction semiconductor device comprising:
 an active region including active p pillars and active n pillars having vertical stripe shapes alternately arranged horizontally in the active region; and island p regions arranged in a matrix form at predetermined intervals in the corners of the active region, the island p regions being arranged in n regions having the same impurity concentration as that of the active n pillars; and   an edge p pillar having a rectangular ring shape with rounded corners surrounding the active region.   
     
     
         30 . The superjunction semiconductor device of  claim 29 , further comprising a termination region including termination n pillars and termination p pillars alternately arranged around the edge p pillar. 
     
     
         31 . A superjunction semiconductor device comprising:
 an active region including active p pillars and active n pillars having vertical stripe shapes alternately arranged horizontally in the active region; and subsidiary p pillars arranged in the active n pillars in corners of the active region, the subsidiary p pillars compensating for an imbalance between the quantity of p charges and the quantity of n charges; and   an edge p pillar having a rectangular ring shape with rounded corners surrounding the active region.   
     
     
         32 . The superjunction semiconductor device of  claim 31 , wherein the subsidiary p pillars have bar shapes vertically arranged in the active n pillars in the corners of the active region. 
     
     
         33 . The superjunction semiconductor device of  claim 31 , wherein the subsidiary p pillars are in the form of islands arranged at predetermined intervals in the active n pillars in the corners of the active region. 
     
     
         34 . The superjunction semiconductor device of  claim 31 , wherein the subsidiary p pillars have bent belt shapes arranged along the inner side of and contacting the edge p pillar in the active n pillars in the corners.