US2012168864A1PendingUtilityA1

Self-aligned well implant for improving short channel effects control, parasitic capacitance, and junction leakage

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Assignee: DENNARD ROBERT HPriority: Sep 28, 2009Filed: Mar 13, 2012Published: Jul 5, 2012
Est. expirySep 28, 2029(~3.2 yrs left)· nominal 20-yr term from priority
H10P 30/222H10D 84/038H10D 84/017H10D 64/017H10D 62/314H10D 30/6757H10D 30/6744H10D 30/797H10D 30/0221H10D 30/0217H10D 30/022H10D 30/0323H10P 30/221
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Claims

Abstract

A transistor device includes a patterned gate structure formed over a substrate, the patterned gate structure including a gate conductor, a gate dielectric layer and sidewall spacers; and a doped well implant formed in the substrate, the well implant being self-aligned with the patterned gate structure.

Claims

exact text as granted — not AI-modified
1 . A transistor device, comprising:
 a patterned gate structure formed over a substrate, the patterned gate structure including a gate conductor, a gate dielectric layer and sidewall spacers; and   a doped well implant formed in the substrate, the well implant being self-aligned with the patterned gate structure.   
     
     
         2 . The transistor device of  claim 1 , wherein the substrate comprises a bulk substrate. 
     
     
         3 . The transistor device of  claim 1 , wherein the substrate comprises a silicon-on-insulator substrate. 
     
     
         4 . The transistor device of  claim 1 , wherein the substrate comprises an undoped channel region beneath the gate dielectric layer, with the self-aligned well implant beneath the channel region. 
     
     
         5 . The transistor device of  claim 4 , further comprising epitaxial semiconductor regions adjacent opposing sides of the channel region and the self-aligned well implant, the epitaxial semiconductor regions corresponding to source and drain regions. 
     
     
         6 . The transistor device of  claim 1 , wherein the self-aligned well implant resides about 5 to about 15 nanometers below a top surface of the substrate. 
     
     
         7 . The transistor device of  claim 1 , wherein the self-aligned well implant has a dopant concentration of about 1×10 19  atoms/cm 3  or less. 
     
     
         8 . The transistor device of  claim 1 , further comprising a halo implant for at least one of the source and drain regions. 
     
     
         9 . The transistor device of  claim 8 , wherein the self-aligned well implant has a dopant concentration of about 1×10 19  atoms/cm 3  or less.

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