Strained mos device and methods for its fabrication

Abstract

A method is provided for fabricating a strained MOS device having a silicon germanium on insulator (SGOI) substrate that includes a layer of monocrystalline silicon germanium material characterized by a first lattice constant. A strained silicon layer is formed over the layer of monocrystalline silicon germanium material. A layer of gate electrode material is patterned to form a gate electrode overlying a channel region. The strained silicon layer is disposed between the gate electrode and the channel region. First recess and second recesses are etched into the layer of monocrystalline silicon germanium material. A layer of monocrystalline semiconductor material is then epitaxially grown to fill the first and second recesses such that it is embedded at the opposing sides of the channel region. The layer of monocrystalline semiconductor material comprises silicon and germanium, and is characterized by a second lattice constant less than the first lattice constant.

1 . A method for fabricating a strained MOS device having a silicon germanium on insulator (SGOI) substrate comprising: a support wafer; an insulating layer overlying the support wafer; and a layer of monocrystalline silicon germanium material characterized by a first lattice constant, the method comprising the steps of:
 forming a strained silicon layer disposed above the layer of monocrystalline silicon germanium material;   forming a gate insulator layer overlying the layer of monocrystalline silicon germanium material;   depositing a layer of gate electrode material overlying the gate insulator layer;   patterning the layer of gate electrode material to form a gate electrode overlying a channel region, the gate electrode having a first sidewall and a second sidewall, the strained silicon layer being disposed between the gate electrode and the channel region;   etching a first recess and a second recess into the monocrystalline semiconductor material, the first recess in alignment with the first sidewall and the second recess in alignment with the second sidewall; and   epitaxially growing a layer of monocrystalline semiconductor material embedded at the opposing sides of the channel region to fill the first recess and the second recess, the layer of monocrystalline semiconductor material comprising silicon and germanium, the layer of monocrystalline semiconductor material characterized by a second lattice constant less than the first lattice constant.   
     
     
         2 . The method of  claim 1  wherein the step of epitaxially growing comprises the step of:
 epitaxially growing a layer of monocrystalline semiconductor material selected from the group consisting of silicon germanium, silicon carbon, and silicon germanium carbon. 
 
     
     
         3 . The method of  claim 1  wherein the layer of monocrystalline silicon germanium material comprises silicon and germanium having a first atomic percentage amount of germanium, and wherein the step of epitaxially growing comprises the step of:
 epitaxially growing a layer of monocrystalline semiconductor material comprising silicon and a second atomic percentage amount of germanium wherein the second atomic percentage amount is less than the first atomic percentage amount. 
 
     
     
         4 . The method of  claim 1 , wherein the strained silicon layer comprises:
 a biaxiallly tensile strained silicon layer that is interposed between the gate electrode and the channel region and that is in contact with the layer of monocrystalline semiconductor material.   
     
     
         5 . A method for fabricating a strained NMOS transistor having a silicon germanium on insulator (SGOI) substrate comprising: a support wafer; an insulating layer overlying the support wafer; and a layer of monocrystalline silicon germanium material characterized by a first lattice constant and comprising germanium present in a first atomic percentage amount, the method comprising the steps of:
 forming a strained silicon layer disposed above the layer of monocrystalline silicon germanium material;   forming a gate electrode overlying the overlying the layer of monocrystalline silicon germanium material, the gate electrode defining a channel in the layer of monocrystalline silicon germanium material, the strained silicon layer being disposed between the gate electrode and the channel;   etching a first recess and a second recess extending into the layer of monocrystalline silicon germanium material, the first recess and the second recess positioned adjacent the channel; and   epitaxially growing a layer of monocrystalline semiconductor material embedded at opposing sides of the channel to fill the first recess and the second recess, the layer of monocrystalline semiconductor material being characterized by a second lattice constant less than the first lattice constant, the layer of monocrystalline semiconductor material comprising silicon and a second atomic percentage amount of germanium that is less than the first atomic percentage amount.   
     
     
         6 . The method of  claim 5 , wherein the step of forming a gate electrode overlying the monocrystalline silicon germanium substrate comprises the steps of:
 forming a gate insulator layer on the monocrystalline silicon germanium substrate;   depositing a layer of gate electrode material overlying the gate insulator layer; and   patterning the layer of gate electrode material to form a gate electrode having a first sidewall and a second sidewall, and   wherein the step of etching a first recess and a second recess extending into the monocrystalline silicon germanium substrate, the first recess and the second recess positioned adjacent the channel comprises the steps of:
 etching a first recess and a second recess into the monocrystalline semiconductor substrate, the first recess and the second recess positioned adjacent the channel, the first recess in alignment with the first sidewall and the second recess in alignment with the second sidewall. 
   
     
     
         7 . The method of  claim 5 , further comprising the steps of:
 depositing a layer of spacer forming material;   applying a layer of photoresist overlying the layer of spacer forming material;   patterning the layer of photoresist to expose a selected portion of the layer of spacer forming material;   anisotropically etching the selected portion of the layer of spacer forming material to form spacers on the first sidewall and the second sidewall, and   wherein the step of etching comprises the step of:   etching the first recess and the second recess using the spacers as an etch mask.   
     
     
         8 . A method for fabricating a strained MOS device having a silicon germanium on insulator (SGOI) substrate comprising: a support wafer; an insulating layer overlying the support wafer; and a layer of monocrystalline silicon germanium material characterized by a first lattice constant, the method comprising the steps of:
 forming a strained silicon layer disposed above the layer of monocrystalline silicon germanium material;   forming a first P-type impurity region including a first channel region having opposing sides in the layer of monocrystalline silicon germanium material and a second N-type impurity region including a second channel region having opposing sides in the layer of monocrystalline silicon germanium material;   patterning a first gate electrode overlying the first channel region, and a second gate electrode overlying the second channel region, the strained silicon layer being disposed between the first gate electrode and the first channel region;   etching first and second recesses in self alignment with the first gate electrode;   etching third and fourth recesses in self alignment with the second gate electrode;   selectively growing a layer of first monocrystalline semiconductor material embedded at the opposing sides of the first channel, the first monocrystalline semiconductor material comprising silicon and germanium, the first monocrystalline semiconductor material characterized by a second lattice constant less than the first lattice constant to fill the first and second recesses; and   selectively growing a layer of second monocrystalline semiconductor material embedded at the opposing sides of the second channel, the second monocrystalline semiconductor material having characterized by a third lattice constant greater than the first lattice constant to fill the third and fourth recesses.   
     
     
         9 . The method of  claim 8  wherein the step of selectively growing a layer of first monocrystalline semiconductor material comprises the step of:
 growing a layer comprising a material selected from the group consisting of silicon, silicon germanium, silicon carbon, and silicon germanium carbon. 
 
     
     
         10 . The method of  claim 9  wherein the layer of monocrystalline silicon germanium material comprises silicon and germanium having a first atomic percentage of germanium, and wherein the step of selectively growing a layer of first monocrystalline semiconductor material comprises:
 growing a layer comprising a material selected from the group consisting of silicon carbon, silicon germanium carbon, and silicon and a second atomic percentage of germanium, wherein the second atomic percentage is less than the first atomic percentage, and wherein the second monocrystalline semiconductor material comprises silicon and germanium having a third atomic percentage of germanium, the third atomic percentage being greater than the first atomic percentage. 
 
     
     
         11 . The method of  claim 8 , wherein the step of selectively growing a layer of second monocrystalline semiconductor material comprises the step of:
 growing a layer of epitaxial silicon germanium.   
     
     
         12 . The method of  claim 8 , wherein the monocrystalline semiconductor substrate comprises silicon and a first atomic percentage of germanium and wherein the step of selectively growing a layer of second monocrystalline semiconductor material comprises the step of growing a layer comprising silicon and a second atomic percentage of germanium wherein the second atomic percentage is greater than the first atomic percentage. 
     
     
         13 . The method of  claim 8  further comprising the steps of:
 ion implanting N-type conductivity determining ions into the layer of first monocrystalline semiconductor material to form N-type source and drain regions; and 
 ion implanting P-type conductivity determining ions into the layer of second monocrystalline semiconductor material to form P-type source and drain regions. 
 
     
     
         14 . The method of  claim 8 , wherein the first monocrystalline semiconductor material further comprises carbon. 
     
     
         15 . The method of  claim 8 , wherein the layer of monocrystalline silicon germanium material comprises silicon and between about 10 and 30 atomic percent germanium. 
     
     
         16 . The method of  claim 8 , wherein the strained silicon layer is interposed between the gate electrode and the first channel region and overlies a portion of the surface of the first P-type region. 
     
     
         17 . The method of  claim 16 , wherein the strained silicon layer overlies a portion of the surface of the first P-type region, and further comprising:
 forming a gate insulator layer disposed overlying the strained silicon layer, wherein the gate insulator layer is disposed under the first gate electrode; and   forming oxide layers formed on sidewalls of the gate electrode;   forming a first spacer adjacent one of the oxide layers and adjacent the first gate electrode and overlying the strained silicon layer, the first spacer being in physical contact with the gate insulator layer and a portion of the first monocrystalline semiconductor material, and a second spacer adjacent the first spacer and overlying the portion of the first monocrystalline semiconductor material; and   forming a liner layer interposed between the one of the oxide layers and the first spacer.   
     
     
         18 . The method of  claim 8 , further comprising:
 forming heavily doped source and drain regions in the first P-type region of the first monocrystalline semiconductor material at the opposing sides of the first channel; and   forming implanted source and drain buffer regions in the layer of monocrystalline silicon germanium material,   wherein the implanted source and drain buffer regions underlie the heavily doped source and drain regions in the first P-type region at the opposing sides of the first channel, the implanted source and drain buffer regions extending through the layer of monocrystalline silicon germanium material to the insulating layer.   
     
     
         19 . The method of  claim 8 , wherein the strained silicon layer comprises a biaxiallly tensile strained silicon layer that overlies a portion of the surface of the first P-type impurity region, and that is in contact with the first monocrystalline semiconductor material. 
     
     
         20 . The method of  claim 8 , wherein the step of selectively growing a layer of first monocrystalline semiconductor material, comprises the step of:
 epitaxially growing the layer of first monocrystalline semiconductor material embedded at the opposing sides of the first channel, the first monocrystalline semiconductor material comprising silicon and germanium, the first monocrystalline semiconductor material characterized by the second lattice constant less than the first lattice constant to fill the first and second recesses, and   wherein the step of selectively growing a layer of second monocrystalline semiconductor material, comprises the step of:   epitaxially growing the layer of second monocrystalline semiconductor material embedded at the opposing sides of the second channel, the second monocrystalline semiconductor material having characterized by the third lattice constant greater than the first lattice constant to fill the third and fourth recesses.