Semiconductor memory device with ferroelectric device and refresh method thereof

Abstract

A semiconductor memory device with a ferroelectric device comprises a channel region, a drain region and a source region formed in a substrate, a ferroelectric layer formed over the channel region, and a word line formed over the ferroelectric layer. A different channel resistance is induced to the channel region depending on a polarity state of the ferroelectric layer, a data read operation is performed by a cell sensing current value differentiated depending on the polarity state of the ferroelectric layer while a read voltage is applied to the word line and a sensing bias voltage is applied to one of the drain region and the source region, and a data write operation is performed by a polarity of the ferroelectric layer changed depending on a voltage applied to the word line, the drain region and the source region.

1 - 4 . (canceled) 
     
     
         5 . A semiconductor memory device comprising:
 a One-Transistor (1-T) Field Effect Transistor (FET) type memory cell including a channel region, a drain region and a source region formed in a substrate;   a ferroelectric layer formed over the channel region; and   a word line formed over the ferroelectric layer, where a different channel resistance is induced to the channel region depending on a polarity state of the ferroelectric layer, wherein the ferroelectric device comprises:   a plurality of word lines arranged in a row direction; and   a plurality of bit lines arranged perpendicularly to the plurality of word lines, and wherein the memory cell is connected between a pair of adjacent bit lines of the plurality of bit lines and configured to read/write data by changing a polarity of the ferroelectric layer depending on voltages applied to the word line and paired bit lines.   
     
     
         6 . The semiconductor memory device according to  claim 5 , wherein the plurality of bit lines include alternately arranged odd bit lines and even bit lines the odd bit lines and the even bit lines being, respectively formed in different layers. 
     
     
         7 . The semiconductor memory device according to  claim 5 , wherein data are read by a cell sensing current value flowing in the paired bit lines while a read voltage is applied to the word line, a sensing bias voltage is applied to one of the paired bit lines and a ground voltage is applied to the other of the paired bit lines in the memory cell. 
     
     
         8 . The semiconductor memory device according to  claim 5 , wherein the memory cell further comprises:
 a sense amplifier configured to amplify data sensed through the plurality of bit lines; and   a register configured to store data amplified by the sense amplifier.   
     
     
         9 . The semiconductor memory device according to  claim 8 , wherein the sense amplifier comprises:
 a column selecting unit configured to selectively connect the register to input/output lines;   an equalizing unit configured to equalize the register;   a pull-up unit configured to pull up both nodes of the register;   an amplifying unit configured to amplify a cell voltage and a reference voltage;   an amplifying activation control unit configured to control activation of the amplifying unit;   a load unit configured to load of the cell voltage and the reference voltage; and   a bias control unit configured to control a current of the plurality of bit lines and a reference current.   
     
     
         10 . The semiconductor memory device according to  claim 8 , further comprising a write driving unit configured to supply data stored in the register or data of the input/output lines to the plurality of bit lines. 
     
     
         11 . The semiconductor memory device according to  claim 5 , wherein a power voltage is applied to the word line and a ground voltage is applied to the paired bit lines when low data are written in the memory cell. 
     
     
         12 . The semiconductor memory device according to  claim 5 , wherein a negative read voltage is applied to the word line and a positive read voltage is applied to the paired bit lines when high data are written in the memory cell. 
     
     
         13 . The semiconductor memory device according to  claim 5 , further comprising a row decoder configured to control a voltage level supplied to the word line depending on an input of a row address. 
     
     
         14 . The semiconductor memory device according to  claim 13 , wherein the row decoder comprises:
 a row address decoder unit configured to output configured to output an enable signal depending on the row address;   a voltage supply unit configured to supply a corresponding voltage to the word line in response to a voltage control signal; and   a word line driving unit configured to control a voltage level of the word line depending on a voltage applied to the voltage supply unit in response to the enable signal.   
     
     
         15 . A semiconductor memory device with a ferroelectric device, the memory device comprising:
 a One-Transistor (1-T) Field Effect Transistor (FET) type memory cell including a channel region, a drain region and a source region formed in a substrate;   a ferroelectric layer formed over the channel region;   a word line formed over the ferroelectric layer, where in different channel resistances are induced to the channel region depending on a polarity state of the ferroelectric layer;   a plurality of word lines arranged in a row direction;   a plurality of bit lines arranged perpendicularly to the plurality of word lines; and   a refresh control unit configured to perform a refresh operation with a specific refresh cycle in order to improve a retaining characteristic of data stored in the memory cell,   wherein the memory cell is connected between a pair of adjacent bit lines of the plurality of bit lines and configured to read/write data by changing a polarity of the ferroelectric layer depending on voltages applied to the word line and paired bit lines.   
     
     
         16 . The semiconductor memory device according to  claim 15 , wherein the refresh control signal generating unit comprises:
 a refresh state information register configured to store nonvolatile parameter information for controlling the refresh operation and output a refresh control signal;   a refresh control signal generating unit configured to output a refresh signal and a refresh enable signal for performing a refresh operation in response to the refresh control signal;   a refresh counter configured to count a refresh cycle in response to the refresh signal so as to output a count address; and   a row address register configured to select the count address in response to the refresh enable signal so as to output the count address into the row decoder.   
     
     
         17 . The semiconductor memory device according to  claim 15 , further comprising a register configured to supply refresh data to the memory cell. 
     
     
         18 . The semiconductor memory device according to  claim 17 , further comprising a column timing logic configured to activate the register in the refresh operation. 
     
     
         19 . A refresh method of a semiconductor memory device with a ferroelectric device, the memory device comprising: a plurality of word lines arranged in a row direction; a plurality of bit lines arranged perpendicularly to the plurality of word lines; and a One-Transistor (1-T) Field Effect Transistor (FET) type memory cell including a channel region, a drain region and a source region formed in a substrate; a ferroelectric layer formed over the channel region; and a word line formed over the ferroelectric layer, where in a polarity state of the ferroelectric layer is changed depending on a voltage applied to the word line and a pair of bit lines connected to the memory cell, the method comprising:
 inducing a different channel resistance to the channel region of the 1T-FET type memory cell to read and/or write data; and   refreshing data stored in the memory cell with a specific refresh cycle in order to improve a retaining characteristic of data stored in the memory cell.   
     
     
         20 . The method according to  claim 19 , wherein the refreshing step includes: reading the data stored in the memory cell to store the data in a register; writing low data in the memory cell; and writing data stored in the register in the memory cell to retain low data stored in the memory cell or to write high data in the memory cell. 
     
     
         21 - 25 . (canceled)