Pre-gate, source/drain strain layer formation

Abstract

A method produces a transistor. The method forms a strain-producing layer on a base layer and then removes at least one portion of the strain-producing layer to create at least one opening in the strain-producing layer. This leaves first and second portions of the strain-producing layer on the substrate. The first and second portions of the strain-producing layer comprise source and drain stressor regions of the transistor. The method then grows a channel region in the opening of the strain-producing layer from the base layer, forms a gate insulator on the channel region, and forms a gate conductor on the gate insulator.

1 . A transistor structure comprising:
 a substrate;   a base layer on said substrate;   epitaxially grown source and drain stressor regions on said base layer;   an epitaxially grown channel region on said base layer between said source and drain stressor regions;   a gate insulator on said channel region; and   a gate conductor on said gate insulator,   said source and drain stressor regions being positioned partially below said gate conductor, and   said source and drain stressor regions having vertical sidewalls below said gate conductor.   
     
     
         2 . The transistor structure according to  claim 1 , said channel region comprising doping concentrations. 
     
     
         3 . The transistor structure according to  claim 1 , said channel region comprising a lower layer of SiC and an upper layer of Si. 
     
     
         4 . The transistor structure according to  claim 1 , further comprising shallow trench isolation regions adjacent said source and drain stressor regions. 
     
     
         5 . The transistor structure according to  claim 1 , said strain-producing layer comprising one of SiGe or SiC. 
     
     
         6 . The transistor structure according to  claim 1 , said vertical sidewalls of said source and drain stressor regions being perpendicular to the plane of said gate insulator. 
     
     
         7 . A transistor structure comprising:
 a substrate;   a base layer on said substrate;   epitaxially grown source and drain stressor regions on said base layer;   an epitaxially grown channel region on said base layer between said source and drain stressor regions;   a gate insulator on said channel region; and   a gate conductor on said gate insulator,   said source and drain stressor regions being positioned partially below said gate conductor, and   said source and drain stressor regions having vertical sidewalls free of epitaxial facets below said gate conductor.   
     
     
         8 . The transistor structure according to  claim 7 , said channel region comprising doping concentrations. 
     
     
         9 . The transistor structure according to  claim 7 , said channel region comprising a lower layer of SiC and an upper layer of Si. 
     
     
         10 . The transistor structure according to  claim 7 , further comprising shallow trench isolation regions adjacent said source and drain stressor regions. 
     
     
         11 . The transistor structure according to  claim 7 , said strain-producing layer comprising one of SiGe or SiC. 
     
     
         12 . The transistor structure according to  claim 7 , said vertical sidewalls of said source and drain stressor regions being perpendicular to the plane of said gate insulator. 
     
     
         13 . A transistor structure comprising:
 a substrate;   a base layer on said substrate;   epitaxially grown source and drain stressor regions on said base layer;   an epitaxially grown channel region on said base layer between said source and drain stressor regions;   a gate insulator on said channel region; and   a gate conductor on said gate insulator,   said source and drain stressor regions being positioned partially below said gate conductor,   said source and drain stressor regions having vertical sidewalls free of epitaxial facets below said gate conductor, and   said source and drain stressor regions having dimensions independent of dimensions of said gate conductor.   
     
     
         14 . The transistor structure according to  claim 13 , said channel region comprising doping concentrations. 
     
     
         15 . The transistor structure according to  claim 13 , said channel region comprising a lower layer of SiC and an upper layer of Si. 
     
     
         16 . The transistor structure according to  claim 13 , further comprising shallow trench isolation regions adjacent said source and drain stressor regions. 
     
     
         17 . The transistor structure according to  claim 13 , said strain-producing layer comprising one of SiGe or SiC. 
     
     
         18 . The transistor structure according to  claim 13 , said vertical sidewalls of said source and drain stressor regions being perpendicular to the plane of said gate insulator.