Scalable Unified Memory Architecture

Abstract

A memory architecture includes a memory controller coupled to multiple modules. Each module includes a computing engine coupled to a shared memory. Each computing engine is capable of receiving instructions from the memory controller and processing the received instructions. The shared memory is configured to store main memory data and graphical data. Certain computing engines are capable of processing graphical data. The memory controller may include a graphics controller that provides instructions to the computing engine. An interconnect on each module allows multiple modules to be coupled to the memory controller.

1 . A system comprising:
 a processor subsystem;   at least one main memory interconnect coupled to the processor subsystem; and   a plurality of memory modules coupled to the main memory interconnect, at least one memory module in the plurality storing execution instructions for the processor subsystem, and at least one memory module in the plurality further comprising a computing engine to perform processing tasks, using memory located on that memory module.   
     
     
         2 . The system of  claim 1 , wherein the processor subsystem includes a central processing unit to execute first instructions that reference first data; a memory controller coupled to the central processing unit to communicate the first instructions and the first data; and a graphics controller coupled to the central processing unit to process graphical data. 
     
     
         3 . The system of  claim 2 , wherein a first memory module in the plurality includes a first integrated-circuit computing engine coupled to the subsystem to receive the first data; and first integrated-circuit memory coupled to the integrated-circuit computing engine to store the first data; and wherein the first integrated-circuit computing engine writes the first data to the first integrated-circuit memory and reads the first data from the first integrated-circuit memory. 
     
     
         4 . The system of  claim 3 , wherein a second memory module in the plurality includes a second integrated-circuit computing engine coupled to the subsystem to execute second instructions conveyed from at least one of the central processing unit, the memory controller, and the graphics controller, the second integrated-circuit computing engine to process second data responsive to the second instructions; and second integrated-circuit memory coupled to the second integrated-circuit computing engine to store the second data. 
     
     
         5 . The system of  claim 4 , further wherein the main memory interconnect conveys the first data to the first memory module and the second instructions to the second memory module. 
     
     
         6 . The system of  claim 5 , wherein the first and second memory modules are interconnected by the main memory interconnect. 
     
     
         7 . The system of  claim 4 , wherein the graphics controller distributes the second instructions to the second module. 
     
     
         8 . The system of  claim 4 , wherein the second instructions include graphics instructions. 
     
     
         9 . The system of  claim 4 , wherein the second instructions include at least one of floating-point instructions, digital signal processing instructions, data compression instructions, and data decompression instructions. 
     
     
         10 . The system of  claim 2 , wherein the central processing unit, the memory controller, and the graphics controller are instantiated on a plurality of integrated circuits. 
     
     
         11 . The system of  claim 2 , wherein at least two of the central processing unit, the memory controller, and the graphics controller are instantiated on one integrated circuit. 
     
     
         12 . The system of  claim 1 , wherein the at least one main memory interconnect includes point-to-point interconnects extending between the subsystem and respective ones of the memory modules. 
     
     
         13 . The system of  claim 1 , wherein the processor subsystem divides image processing tasks into different portions and conveys the portions to respective ones of the memory modules. 
     
     
         14 . The system of  claim 13 , wherein the processor subsystem references each of the portions to a respective display area. 
     
     
         15 . A memory module for storing main-memory instructions executed by a central processing unit and referencing first data, the memory module comprising:
 first integrated-circuit memory to store the main-memory instructions and the first data;   second integrated-circuit memory to store second instructions and second data; and   an integrated-circuit computing engine coupled to the first and second integrated-circuit memories, the integrated-circuit computing engine to convey the instructions and first data between the central processing unit and the first integrated-circuit memory and to execute the second instructions with reference to the second data.   
     
     
         16 . The memory module of  claim 15 , wherein the first integrated-circuit memory consists of one or more first memory integrated circuits and the second integrated-circuit memory consists of one or more second memory integrated circuits separate from the first memory integrated circuits. 
     
     
         17 . The memory module of  claim 15 , wherein the integrated-circuit computing engine uses the second instructions and second data to process graphical images. 
     
     
         18 . The memory module of  claim 15 , wherein the integrated-circuit computing engine uses the second instructions and second data to process floating-point instructions. 
     
     
         19 . The memory module of  claim 15 , wherein the integrated-circuit computing engine performs at least one of digital signal processing, data compression, and data decompression on the second data responsive to the second instructions. 
     
     
         20 . The memory module of  claim 19 , wherein the integrated-circuit computing engine further performs image processing responsive to the second instructions.