Nanowire mosfet with doped epitaxial contacts for source and drain

Abstract

A FET structure with a nanowire forming the FET channel, and doped source and drain regions formed by radial epitaxy from the nanowire body is disclosed. A top gated and a bottom gated nanowire FET structures are discussed. The source and drain fabrication can use either selective or non-selective epitaxy.

1 . A method of forming a semiconductor structure comprising:
 forming an insulating layer over a host substrate;   growing semiconductor nanowires over said insulating layer;   depositing a gate dielectric on said semiconductor nanowires;   forming a top gate on a portion of said gate dielectric;   forming spacers on sidewalls of said top gate;   removing a portion of said gate dielectric that is not covered by said top gate and said spacers to expose a portion of said semiconductor nanowires; and   growing a semiconductor material from said exposed portion of said semiconductor nanowires by radial epitaxy.   
     
     
         2 . The method of  claim 1  wherein said radial epitaxy includes in-situ doping. 
     
     
         3 . The method of  claim 1  further comprising implanting the semiconductor material with a dopant. 
     
     
         4 . The method of  claim 1  wherein said semiconductor nanowires are non-doped. 
     
     
         5 . The method of  claim 1  wherein said growing the semiconductor nanowires comprises catalytic growth. 
     
     
         6 . The method of  claim 5  wherein said catalytic growth includes chemical vapor deposition or plasma enhanced chemical vapor deposition. 
     
     
         7 . The method of  claim 1  wherein said semiconductor nanowires are silicon semiconductor nanowires. 
     
     
         8 . The method of  claim 1  further comprising siliciding a portion of the semiconductor material forming a layer of silicide located on a topmost surface of the semiconductor material. 
     
     
         9 . The method of  claim 1  further comprising forming a metal contact on said layer of silicide. 
     
     
         10 . The method of  claim 1  wherein said semiconductor material has a portion that entirely covers a vertical sidewall portion of said semiconductor nanowire. 
     
     
         11 . The method of  claim 1  wherein said depositing the gate dielectric comprises thermal growth. 
     
     
         12 . The method of  claim 1  wherein said depositing the gate dielectric on said semiconductor nanowires provides semiconductor nanowires that are completely coated with said gate dielectric. 
     
     
         13 . The method of  claim 1  wherein said semiconductor material includes a different semiconductor material as compared to the semiconductor nanowires. 
     
     
         14 . The method of  claim 1  wherein said semiconductor nanowire forms a channel of a device, and said semiconductor material forms a source/drain region of said device. 
     
     
         15 . The method of  claim 1  wherein after removing the portion of said gate dielectric that is not covered by said top gate and said spacers to expose a portion of said semiconductor nanowires, the gate dielectric portion atop each semiconductor nanowire has a length that is less than a length of a gate dielectric portion that is located beneath each semiconductor nanowire. 
     
     
         16 . The method of  claim 15  wherein each semiconductor nanowire has a length that is the same as that of the gate dielectric portion that is located beneath each semiconductor nanowire. 
     
     
         17 . The method of  claim 1  wherein said semiconductor material has a bottommost surface that is coplanar with a bottommost surface of each semiconductor nanowire. 
     
     
         18 . The method of  claim 17  wherein said semiconductor material does not extend onto a vertical edge of a gate dielectric portion that is located beneath each semiconductor nanowire. 
     
     
         19 . The method of  claim 1  wherein a mask is formed on an uppermost surface of said top gate prior to forming said spacers. 
     
     
         20 . The method of  claim 1  wherein forming the top gate comprises depositing a gate conductor and a hard mask, and patterning the gate conductor and hard mask by lithography and etching.