Methods of Forming Dual-Damascene Metal Wiring Patterns for Integrated Circuit Devices and Wiring Patterns Formed Thereby

Abstract

Methods of forming dual-damascene metal wiring patterns include forming a first metal wiring pattern (e.g., copper wiring pattern) on an integrated circuit substrate and forming an etch-stop layer on the first metal wiring pattern. These steps are followed by the steps of forming an electrically insulating layer on the etch-stop layer and forming an inter-metal dielectric layer on the electrically insulating layer. The inter-metal dielectric layer and the electrically insulating layer are selectively etched in sequence to define an opening therein that exposes a first portion of the etch-stop layer. This opening may include a trench and a via hole extending downward from a bottom of the trench. A first barrier metal layer is formed on a sidewall of the opening and directly on the first portion of the etch-stop layer. A portion of the first barrier metal layer is selectively removed from the first portion of the etch-stop layer. The first portion of the etch-stop layer is then selectively etched for a sufficient duration to expose a portion of the first metal wiring pattern. A second metal wiring pattern is formed in the opening in order to complete a dual-damascene structure.

1 . A method of forming an integrated circuit, comprising the steps of:
 forming a first metal wiring pattern on an integrated circuit substrate;   forming an etch-stop layer on the first metal wiring pattern;   forming an electrically insulating layer on the etch-stop layer;   forming an inter-metal dielectric layer on the electrically insulating layer;   selectively etching the inter-metal dielectric layer and the electrically insulating layer in sequence to define an opening therein that exposes a first portion of the etch-stop layer;   forming a first barrier metal layer on a sidewall of the opening and directly on the first portion of the etch-stop layer;   selectively removing a portion of the first barrier metal layer from the first portion of the etch-stop layer; then   selectively etching the first portion of the etch-stop layer for a sufficient duration to expose a portion of the first metal wiring pattern, using the first barrier metal layer as an etching mask; and then   forming a second metal wiring pattern in the opening.   
     
     
         2 . The method of  claim 1 , wherein said step of forming a second metal wiring pattern is preceded by a step of forming a second barrier metal layer on the sidewall of the opening and on the exposed portion of the first metal wiring pattern. 
     
     
         3 . The method of  claim 2 , wherein said step of forming a second barrier metal layer is followed by a step of selectively etching a portion of the second barrier metal layer for a sufficient duration to expose the portion of the first metal wiring pattern. 
     
     
         4 . The method of  claim 2 , wherein said step of forming a second barrier metal layer is followed by a step of selectively etching a portion of the second barrier metal layer and the first metal wiring pattern in sequence to define a recess within an upper surface of the first metal wiring pattern. 
     
     
         5 . The method of  claim 4 , wherein said step of forming a second metal wiring pattern is preceded by a step of forming a third barrier metal layer on the recess within the first metal wiring pattern. 
     
     
         6 . The method of  claim 1 , wherein said step of forming an etch-stop layer comprises forming a SiCN layer having a thickness in a range from about 200 Å to about 1,000 Å on the first metal wiring pattern. 
     
     
         7 . The method of  claim 1 , wherein said step of forming an inter-metal dielectric layer comprises forming a SiCOH layer having a thickness in a range from about 2,000 Å to about 10,000 Å on the electrically insulating layer. 
     
     
         8 . The method of  claim 1 , wherein said step of forming a first barrier metal layer comprises forming a metal layer comprising tantalum on the sidewall of the opening and directly on the first portion of the etch-stop layer. 
     
     
         9 . The method of  claim 1 , wherein said step of forming a second metal wiring pattern is preceded by a step of exposing the first metal wiring pattern to a diluted HF cleaning solution. 
     
     
         10 . A method of forming an integrated circuit device, comprising the steps of:
 forming a first electrically conductive wiring pattern on an integrated circuit substrate;   forming first and second electrically insulating layers of different material type on the first electrically conductive wiring pattern;   selectively etching the second electrically insulating layer for a sufficient duration to define an opening therein that exposes a portion of the first electrically insulating layer;   forming a first barrier metal layer on a sidewall of the opening and directly on the portion of the first electrically insulating layer;   selectively removing a portion of the first barrier metal layer from the portion of the first electrically insulating layer; then   selectively etching the portion of the first electrically insulating layer for a sufficient duration to expose a portion of the first electrically conductive wiring pattern, using the first barrier metal layer as an etching mask; and then   forming a second electrically conductive wiring pattern in the opening.   
     
     
         11 . The method of  claim 10 , wherein the first electrically insulating layer is a SiCN layer having a thickness in a range from about 200 Å to about 1,000 Å. 
     
     
         12 . The method of  claim 11 , wherein the second electrically insulating layer is a SiCOH layer having a thickness in a range from about 2,000 Å to about 10,000 Å. 
     
     
         13 . The method of  claim 12 , wherein the first barrier metal layer is a metal layer comprising tantalum and having a thickness in a range from about 30 Å to about 100 Å. 
     
     
         14 . The method of  claim 10 , wherein said step of forming a second electrically conductive wiring pattern is preceded by the step of forming a second barrier metal layer comprising tantalum on the exposed portion of the first electrically conductive wiring pattern. 
     
     
         15 . A method of forming an integrated circuit, comprising the steps of:
 forming a first copper wiring pattern on an integrated circuit substrate;   forming an etch-stop layer comprising SiCN on the first copper wiring pattern;   forming a silicon dioxide layer having a thickness in a range from about 100 Å to about 500 Å on the etch-stop layer;   forming an inter-metal dielectric layer comprising SiCOH on the silicon dioxide layer;   selectively etching the inter-metal dielectric layer and the silicon dioxide layer in sequence to define an opening therein that exposes a first portion of the etch-stop layer;   forming a first barrier metal layer comprising tantalum on a sidewall of the opening and directly on the first portion of the etch-stop layer;   selectively removing a portion of the first barrier metal layer from the first portion of the etch-stop layer; then   selectively etching the first portion of the etch-stop layer for a sufficient duration to expose a portion of the first copper wiring pattern, using the first barrier metal layer as an etching mask;   forming a second barrier metal layer comprising tantalum that extends on the first barrier metal layer, a sidewall of the etch-stop layer and the exposed portion of the first copper wiring pattern;   selectively etching the second barrier metal layer to expose the first copper wiring pattern; then   forming a third barrier metal layer comprising tantalum on the second barrier metal layer and on the first copper wiring pattern; and then   filling the opening with a second copper wiring pattern.   
     
     
         16 . The method of  claim 15 , wherein said step of selectively etching the inter-metal dielectric layer and the silicon dioxide layer in sequence is preceded by a step of forming a silicon dioxide hard mask layer on the inter-metal dielectric layer. 
     
     
         17 . The method of  claim 15 , wherein said step of forming an etch-stop layer comprises forming a SiCN layer having a thickness in a range from about 100 Å to about 500 Å, on the first copper wiring pattern.