Method and system for utilizing perovskite material for charge storage and as a dielectric

Abstract

A memory device is disclosed. In a first aspect the memory comprises a first doped awell; two wells of opposite doping implanted in the first doped well; and two bitlines located on top of the two wells. The memory includes a Perovsite material on top of the first doped well and located between two bitlines; and a wordline located above the Perovskite material. In a second aspect the memory comprises a first doped well; two wells of opposite doping implanted in the first doped well; and two bitlines located on top of the two wells. The memory includes a Perovskite material located within one of the bitlines and a wordline located above the first doped well and located between the two bitlines.

1 . A memory comprising:
 a first doped well;   two wells of opposite doping implanted in the first doped well;   two bitlines located on top of the two wells;   a Perovskite material on top of the first doped well and located between two biltines; and   a wordline located above the Perovskite material.   
     
     
         2 . The memory of  claim 1 , wherein the first doped well comprises a Pwell and the two wells comprise two Nwells. 
     
     
         3 . The memory of  claim 1 , wherein the first doped well comprises an Nwell and the two wells comprise two Pwells. 
     
     
         4 . The memory of  claim 1 , wherein the Perovskite material comprises a PCMO layer. 
     
     
         5 . A memory comprising:
 a first doped well;   two Nwells implanted in the Pwell;   two bitlines located on top of the two Nwells;   a Perovskite material located within one of the two Nwells; and   a wordline located between the two bitlines.   
     
     
         6 . The memory of  claim 5 , wherein the first doped well comprises a Pwell and the two wells comprises two Nwells. 
     
     
         7 . The memory of  claim 5 , wherein the first doped well comprises an Nwell and the two wells comprise two Pwells. 
     
     
         8 . The memory of  claim 5 , wherein the Perovskite material comprises a PCMO layer. 
     
     
         9 . A system comprising one or more of the memory of  claim 1 . 
     
     
         10 . A system comprising one or more of the memory of  claim 5 . 
     
     
         11 . A memory comprising:
 a first doped well;   two wells of opposite doping implanted in the first doped well;   two bitlines located on top of the two wells;   a Perovskite material connected to one of the bitlines; and   a wordline located above the two wells of opposite doping.   
     
     
         12 . The memory of  claim 11 , wherein the first doped well comprises a Pwell and the two wells comprise two Nwells. 
     
     
         13 . The memory of  claim 11 , wherein the first doped well comprises an Nwell and the two wells comprise two Pwells. 
     
     
         14 . The memory of  claim 11 , wherein the Perovskite material comprises a PCMO layer. 
     
     
         15 . A system comprising one or more of the memory of  claim 11 . 
     
     
         16 . A method for providing a memory, comprising
 providing a transistor;   providing a capacitor comprising Perovskite material, wherein the capacitor is connected to a side of the transistor;   providing a wordline, connected to a gate of the transistor;   providing a bitline, connected to a side of the transistor not connected to the capacitor; and   providing a driveline, connected to the capacitor.   
     
     
         17 . The method of  claim 16 , comprising
 writing the memory by:   applying a positive voltage to the bitline;   connecting the driveline to ground; and   asserting the wordline.   
     
     
         18 . The method of  claim 16 , comprising
 writing the memory by:   applying a positive voltage to the driveline;   connecting the bitline to ground; and   asserting the wordline.   
     
     
         19 . The method of  claim 16 , comprising
 reading the memory by:   floating the bitline;   applying a positive voltage to the driveline; and   asserting the wordline.   
     
     
         20 . A circuit for a memory, comprising
 a transistor;   a capacitor comprising Perovskite material, wherein the capacitor is connected to a side of the transistor;   a wordline, connected to a gate of the transistor;   a bitline, connected to a side of the transistor not connected to the capacitor; and   a driveline, connected to the capacitor.