Universal inter-layer interconnect for multi-layer semiconductor stacks

Abstract

An apparatus, program product and method facilitate the design of a multi-layer circuit arrangement incorporating a universal, standardized inter-layer interconnect in a multi-layer semiconductor stack to facilitate interconnection and communication between functional units disposed on a stack of semiconductor dies. Each circuit layer in the multi-layer semiconductor stack is required to include an inter-layer interface region that is disposed at substantially the same topographic location such that when the semiconductor dies upon which such circuit layers are disposed are arranged together in a stack, electrical conductors disposed within each semiconductor die are aligned with one another to provide an inter-layer bus that is oriented vertically, or transversely, with respect to the individual circuit layers.

1 . A computer-implemented method of designing a multi-layer circuit arrangement, the method comprising:
 allocating each of a plurality of functional units in the circuit arrangement to one of a plurality of circuit layers based upon a functional characteristic thereof;   in response to user input, laying out each functional unit on the respective circuit layer to which such functional unit is allocated, wherein each circuit layer defines circuit logic configured to be integrated onto a semiconductor die, and wherein each circuit layer includes an inter-layer interface region disposed at a predefined topographic location thereon such that the inter-layer interface regions on the plurality of circuit layers are disposed at substantially the same topographic location when the respective semiconductor dies are physically and electrically coupled to one another in a stack, and wherein each inter-layer interface region includes a plurality of signal paths that are configured to define an inter-layer bus that electrically interconnects the plurality of circuit layers to one another when the respective semiconductor dies are physically and electrically coupled to one another in the stack; and   in response to user input, interconnecting each functional unit to at least a subset of the plurality of signal paths in the inter-layer interface region of the circuit layer allocated thereto.   
     
     
         2 . The method of  claim 1 , wherein laying out each functional unit and interconnecting each functional unit include generating at least one design file describing the plurality of circuit layers, the method further comprising manufacturing the circuit arrangement using the at least one design file, wherein manufacturing the circuit arrangement includes fabricating a plurality of semiconductor dies with the plurality of circuit layers defined thereon, and physically and electrically coupling the semiconductor dies to one another in a stack such that the inter-layer interface regions of the respective circuit layers are topographically aligned and the functional units defined on the plurality of circuit layers are electrically coupled to one another via the inter-layer bus. 
     
     
         3 . The method of  claim 1 , wherein each circuit layer is based upon a circuit layer template having the inter-layer interface region defined at a predefined topographical location thereon. 
     
     
         4 . The method of  claim 1 , wherein the inter-layer bus comprises a plurality of bus segments extending through the plurality of circuit layers, each bus segment disposed at a different topographical location, and wherein at least one circuit layer includes an intra-layer bus defined therein and configured to electrically couple the plurality of bus segments to one another. 
     
     
         5 . The method of  claim 1 , wherein the plurality of circuit layers are designed using the same semiconductor fabrication design rules. 
     
     
         6 . The method of  claim 1 , wherein at least one circuit layer is designed using different semiconductor fabrication design rules from another circuit layer. 
     
     
         7 . The method of  claim 1 , wherein the plurality of functional units are associated with a single-layer circuit arrangement, and wherein the method comprises adapting the single-layer circuit arrangement into the multi-layer circuit arrangement. 
     
     
         8 . The method of  claim 1 , wherein allocating each functional unit to a circuit layer includes allocating a plurality of processor functional units to at least one compute circuit layer and allocating a plurality of accelerator functional units to at least one accelerator circuit layer. 
     
     
         9 . The method of  claim 8 , wherein allocating each functional unit to a circuit layer further includes allocating a memory controller functional unit and at least one external interface functional unit to an I/O circuit layer that additionally includes external interfaces for interfacing the circuit arrangement with at least one external device. 
     
     
         10 . The method of  claim 1 , wherein the plurality of signal paths comprises a plurality of functional bus signal paths and a plurality of pervasive signal paths. 
     
     
         11 . An apparatus, comprising:
 at least one processor; and   program code configured upon execution by the at least one processor to design a multi-layer circuit arrangement by:
 allocating each of a plurality of functional units in the circuit arrangement to one of a plurality of circuit layers based upon a functional characteristic thereof; 
 in response to user input, laying out each functional unit on the respective circuit layer to which such functional unit is allocated, wherein each circuit layer defines circuit logic configured to be integrated onto a semiconductor die, and wherein each circuit layer includes an inter-layer interface region disposed at a predefined topographic location thereon such that the inter-layer interface regions on the plurality of circuit layers are disposed at substantially the same topographic location when the respective semiconductor dies are physically and electrically coupled to one another in a stack, and wherein each inter-layer interface region includes a plurality of signal paths that are configured to define an inter-layer bus that electrically interconnects the plurality of circuit layers to one another when the respective semiconductor dies are physically and electrically coupled to one another in the stack; and 
 in response to user input, interconnecting each functional unit to at least a subset of the plurality of signal paths in the inter-layer interface region of the circuit layer allocated thereto. 
   
     
     
         12 . A program product, comprising:
 a computer readable medium; and   program code resident on the computer readable medium and configured upon execution to design a multi-layer circuit arrangement by:
 allocating each of a plurality of functional units in the circuit arrangement to one of a plurality of circuit layers based upon a functional characteristic thereof; 
 in response to user input, laying out each functional unit on the respective circuit layer to which such functional unit is allocated, wherein each circuit layer defines circuit logic configured to be integrated onto a semiconductor die, and wherein each circuit layer includes an inter-layer interface region disposed at a predefined topographic location thereon such that the inter-layer interface regions on the plurality of circuit layers are disposed at substantially the same topographic location when the respective semiconductor dies are physically and electrically coupled to one another in a stack, and wherein each inter-layer interface region includes a plurality of signal paths that are configured to define an inter-layer bus that electrically interconnects the plurality of circuit layers to one another when the respective semiconductor dies are physically and electrically coupled to one another in the stack; and 
 in response to user input, interconnecting each functional unit to at least a subset of the plurality of signal paths in the inter-layer interface region of the circuit layer allocated thereto.