Electronic device having stack-type semiconductor package and method of forming the same

Abstract

An electronic device includes a lower electronic part including a lower substrate, a lower chip structure disposed on the lower substrate, and a lower molding layer covering the lower chip structure and having a recessed region in an upper surface of the lower molding layer, and an upper electronic part including an upper substrate disposed on the lower electronic part, and an upper chip structure projecting from the upper substrate, wherein the recessed region of the lower molding layer receives the upper chip structure.

1 . A method of forming an electronic device, comprising:
 forming a lower chip structure on a lower substrate;   forming a lower molding layer on the lower chip structure, wherein the lower molding layer covers the lower chip structure and has a recessed region on an upper surface of the lower molding layer, thereby forming a lower electronic part including the lower substrate, the lower chip structure, and the lower molding layer;   forming an upper electronic part including an upper substrate and an upper chip structure disposed on the upper substrate; and   disposing the upper chip structure into the recessed region of the lower molding layer to combine the upper electronic part with the lower electronic part.   
     
     
         2 . The method of  claim 1 , wherein the lower substrate is a printed circuit board, and the lower chip structure includes a semiconductor chip connected to the lower substrate in a wire bonding structure or in a flip-chip structure. 
     
     
         3 . The method of  claim 1 , wherein the upper substrate is a printed circuit board, and the upper chip structure includes a semiconductor chip connected to the upper substrate in a wire bonding structure or in a flip-chip structure. 
     
     
         4 . The method of  claim 1 , further comprising forming a protection layer covering the upper chip structure on the upper substrate, wherein the protection layer is disposed in the recessed region. 
     
     
         5 . The method of  claim 1 , wherein forming the upper electronic part comprises:
 preparing a printed circuit board having an opening as the upper substrate; and   forming the upper chip structure contacting the printed circuit board around the opening.   
     
     
         6 . The method of  claim 1 , further comprising:
 forming a protection layer filling the opening of the upper substrate, and projecting from a surface opposite to a surface contacting the upper chip structure of the upper substrate;   forming a first electronic part including a first substrate, a first chip structure disposed on the first substrate, and a first molding layer covering the first chip structure and having a first recessed region in an upper surface on the first substrate; and   combining the first electronic part with the upper electronic part so that the protection layer is disposed in the first recessed region of the first electronic part.   
     
     
         7 . The method of  claim 1 , wherein the lower electronic part and the upper electronic part are combined by a connection structure disposed at both sides of the lower and upper chip structures, the connection structure contacting the lower substrate and the upper substrate to electrically connect the lower electronic part to the upper electronic part. 
     
     
         8 . The method of  claim 1 , wherein combining the lower electronic part with the upper electronic part comprises forming a through electrode structure passing through the upper substrate disposed at both sides of the upper chip structure and passing through the lower molding layer disposed at both sides of the lower chip structure to be connected to the lower substrate. 
     
     
         9 . The method of  claim 1 , further comprising forming a ball structure disposed opposite to the lower chip structure with the lower substrate interposed therebetween. 
     
     
         10 . The method of  claim 1 , further comprising stacking a single chip semiconductor package or a multi chip semiconductor package on the upper electronic part. 
     
     
         11 . A stack-type semiconductor package comprising:
 a lower substrate;   a lower chip disposed on the lower substrate;   a lower molding layer disposed on the lower chip, the lower molding layer having a recessed region with a first depth;   an upper substrate;   an upper chip disposed on the upper substrate; and   an upper molding layer disposed on the upper chip,   wherein a substantial portion of the first depth of the recessed region receives the upper molding layer of the upper substrate.