Interconnect structure having a via with a via gouging feature and dielectric liner sidewalls for beol integration

Abstract

An interconnect structure including a lower interconnect level with a first dielectric layer having a first conductive material embedded therein; a dielectric capping layer located on the first dielectric layer and some portions of the first conductive material; an upper interconnect level including a second dielectric layer having at least one via opening filled with a second conductive material and at least one overlying line opening filled with the second conductive material disposed therein, wherein the at least one via opening is in contact with the first conductive material in the lower interconnect level by a via gouging feature; a dielectric liner on sidewalls of the at least one via opening; and a first diffusion barrier layer on sidewalls and a bottom of both the at least one via opening and the at least one overlying line opening. A method of forming the interconnect structure is also provided.

1 . An interconnect structure comprising:
 a lower interconnect level including a first dielectric layer having a first conductive material embedded therein;   a dielectric capping layer located on said first dielectric layer and some, but not all, portions of said first conductive material;   an upper interconnect level including a second dielectric layer having at least one via opening filled with a second conductive material and at least one overlying line opening filled with said second conductive material disposed therein, wherein said at least one via opening is in contact with said first conductive material in said lower interconnect level by a via gouging feature;   a dielectric liner on sidewalls of said at least one via opening; and   a first diffusion barrier layer on sidewalls and a bottom of both said at least one via opening and said at least one overlying line opening.   
     
     
         2 . The interconnect structure of  claim 1 , wherein said dielectric liner is only on said sidewalls of said at least one via opening, but not on said bottom of said at least one via opening and not on said sidewalls and said bottom of said at least one overlying line opening. 
     
     
         3 . The interconnect structure of  claim 1 , wherein said first conductive material is spaced apart from said first dielectric layer by a second diffusion barrier layer. 
     
     
         4 . The interconnect structure of  claim 1 , wherein said upper interconnect level further comprises at least one line opening filled with said second conductive material being away from, and not overlying, said at least one via opening filled with said second conductive material. 
     
     
         5 . The interconnect structure of  claim 1 , wherein said first and second dielectric layers comprise the same or different dielectric material having a dielectric constant of about 4.0 or less. 
     
     
         6 . The interconnect structure of  claim 5 , wherein said first and second dielectric layers have a dielectric constant of about 2.8 or less. 
     
     
         7 . The interconnect structure of  claim 1 , wherein said first conductive material comprises polysilicon, a conductive metal, an alloy of two or more conductive metals, a conductive metal silicide, or a combination comprising two or more of the foregoing materials. 
     
     
         8 . The interconnect structure of  claim 1 , wherein said dielectric capping layer comprises SiC, Si 4 NH 3 , SiO 2 , a carbon doped silicon oxide, a nitrogen and hydrogen doped silicon carbide (SiC(N, H)), or a combination comprising two or more of the foregoing materials. 
     
     
         9 . The interconnect structure of  claim 1 , wherein said dielectric liner layer comprises a dielectric material. 
     
     
         10 . The interconnect structure of  claim 9 , wherein said dielectric liner layer comprises SiO 2 , Si 3 N 4 , SiC, or a nitrogen and hydrogen doped silicon carbide (SiC(N, H)). 
     
     
         11 . The interconnect structure of  claim 1 , wherein said dielectric liner layer has a thickness in the range from about 2 nm to about 100 nm. 
     
     
         12 . The method of  claim 11 , wherein said dielectric liner layer has a thickness in the range from about 5 nm to about 20 nm. 
     
     
         13 . The interconnect structure of  claim 1 , wherein said first diffusion barrier layer comprises Ta, TaN, Ti, TiN, Ru, RuN, RuTa, RuTaN, W, WN, Co, CoW, Mn, MnO, or a combination comprising two or more of the foregoing materials. 
     
     
         14 . The interconnect structure of  claim 1 , further comprising a plating seed layer on top of said first diffusion barrier layer. 
     
     
         15 . The interconnect structure of  claim 14 , wherein said plating seed layer comprises Ru, TaRu, Ir, Rh, Pt, Pd, Co, or an alloy of two or more of the foregoing materials. 
     
     
         16 . The interconnect structure of  claim 1 , wherein second conductive material comprise Cu, Al, W or an alloy comprising two or more of the foregoing metals.