Method for forming a self-aligned isolation structure utilizing sidewall spacers as an etch mask and remaining as a portion of the isolation structure

Abstract

The present invention relates to methods for forming microelectronic structures in a semiconductor substrate. The method includes selectively removing dielectric material to expose a portion of an oxide overlying a semiconductor substrate. Insulating material may be formed substantially conformably over the oxide and remaining portions of the dielectric material. Spacers may be formed from the insulating material. An isolation trench etch follows the spacer etch. An optional thermal oxidation of the surfaces in the isolation trench may be performed, which may optionally be followed by doping of the bottom of the isolation trench to further isolate neighboring active regions on either side of the isolation trench. A conformal material may be formed substantially conformably over the spacer, over the remaining portions of the dielectric material, and substantially filling the isolation trench. Planarization of the conformal material may follow.

1 . A method of forming a microelectronic structure, the method comprising:
 forming spacers initiating upon an oxide, each spacer in contact with exposed lateral portions of an insulative material segment;   forming an isolation trench proximate the spacers and extending below the oxide into an underlying semiconductor substrate;   filling the isolation trench with an insulation film;   removing portions of the insulation film, the insulative material segments and the spacers to form a coplanar surface; and   removing remaining portions of the insulative material segments to expose an upper surface of the semiconductor substrate such that remaining portions of the insulation film and spacers form a microelectronic structure filling the isolation trench, extending laterally away from the isolation trench upon remaining portions of the oxide, and sidewalls of the microelectronic structure initiate on a surface of the remaining portions of the oxide and are substantially perpendicular to a surface of the microelectronic structure.   
     
     
         2 . The method according to  claim 1 , further comprising densifying the insulation film after filling the isolation trench. 
     
     
         3 . The method according to  claim 1 , wherein forming spacers initiating upon an oxide and in contact with exposed lateral portions of an insulative material segment further forming the insulative material segment over an active area of the semiconductor substrate. 
     
     
         4 . The method according to  claim 1 , wherein forming spacers initiating upon an oxide and in contact with exposed lateral portions of an insulative material segment further forming the insulative material segment from a nitride material. 
     
     
         5 . The method according to  claim 1 , wherein forming the spacers and forming the isolation trench are effected substantially simultaneously. 
     
     
         6 . The method according to  claim 1 , further comprising oxidizing the isolation trench to form an insulation liner within the isolation trench. 
     
     
         7 . The method of  claim 1 , further comprising depositing an insulation liner within the isolation trench 
     
     
         8 . The method of  claim 1 , further comprising forming an insulation liner comprising Si 3 N 4  within the isolation trench. 
     
     
         9 . The method of  claim 1 , further comprising doping the isolation trench after forming the isolation trench. 
     
     
         10 . A method of forming an isolation trench, the method comprising:
 forming spacers on laterally exposed portions of a structure including oxide material and polysilicon material underlying insulation material;   forming an isolation trench adjacent to and below the spacers, the isolation trench extending into a semiconductor substrate;   filling the isolation trench with an isolation material;   substantially simultaneously forming a common upper surface of the isolation material, the insulation material and the spacers; and   removing the insulation material to expose the semiconductor substrate such that the isolation material and the pair of spacers form an isolation structure which has a substantially horizontal upper surface and fills the isolation trench, extends away from the isolation trench upon remaining portions of the oxide material, and sidewalls of the isolation structure extend substantially vertically from an upper surface of the oxide material to the upper surface of the isolation structure.   
     
     
         11 . The method according to  claim 10 , further comprising selectively implanting ions into an active area of the semiconductor substrate beneath horizontal sections of the isolation structure. 
     
     
         12 . The method according to  claim 10 , further comprising densifying the isolation material before substantially simultaneously forming a common upper surface of the isolation material, the insulation material and the spacers. 
     
     
         13 . The method according to  claim 10 , wherein substantially simultaneously forming a common upper surface of the isolation material, the insulation material and the spacers comprises planarizing the isolation material, the insulation material and the spacers. 
     
     
         14 . A method of forming a microelectronic structure, the method comprising:
 forming spacers on a dielectric material partially overlying an oxide;   forming an isolation trench proximate the spacers;   filling the isolation trench with an electrically insulative material;   forming a substantially uniform upper surface from the electrically insulative material and the dielectric material; and   removing the dielectric material to expose a portion of an underlying semiconductor substrate such that the electrically insulating material and the spacers form a microelectronic structure comprising the electrically insulative material in the isolation trench substantially orthogonal to horizontal sections of the microelectronic structure that extend away from the isolation trench upon remaining portions of the oxide, and sidewalls of the microelectronic structure initiate on an upper surface of the oxide and are substantially perpendicular to an upper surface of the microelectronic structure.   
     
     
         15 . The method according to  claim 14 , further comprising implanting ions in the semiconductor substrate to form active areas proximate the horizontal sections of the microelectronic structure. 
     
     
         16 . The method according to  claim 14 , wherein an active area of the semiconductor substrate is at least partially covered by the microelectronic structure. 
     
     
         17 . The method according to  claim 14 , further comprising removing the oxide after removing the dielectric material to expose a portion of an underlying semiconductor substrate such that the electrically insulating material and the spacers form a microelectronic structure. 
     
     
         18 . The method according to  claim 17 , further comprising forming a gate oxide after removing the oxide. 
     
     
         19 . The method according to  claim 14 , further comprising forming a liner within the isolation trench. 
     
     
         20 . The method according to  claim 14 , further comprising densifying the electrically insulative material after filling the isolation trench. 
     
     
         21 . The method according to  claim 14 , wherein forming spacers on a dielectric material partially overlying an oxide comprises etching silicon dioxide to form spacers on sidewalls of the dielectric material.