Predicated issue for conditional branch instructions

Abstract

A method and apparatus for executing branch instructions is provided. In one embodiment, the method includes receiving a branch instruction, wherein a first path of the branch instruction branches to a target instruction, and wherein a second path of the branch instruction branches to one or more interceding instructions between the branch instruction and the target instruction. The method further includes issuing the one or more interceding instructions and the target instruction and determining if the branch instruction follows the first path or the second path. Upon determining that the branch instruction follows the first path, the one or more interceding instructions between the branch instruction and the target instruction are invalidated.

1 . A processor comprising:
 a cache; and   circuitry configured to:
 receive a branch instruction from the cache, wherein a first path of the branch instruction branches to a target instruction, and wherein a second path of the branch instruction branches to one or more interceding instructions between the branch instruction and the target instruction; 
 issue the one or more interceding instructions and the target instruction; 
 determine if the branch instruction follows the first path or the second path; and 
 upon determining that the branch instruction follows the first path, invalidate the one or more interceding instructions between the branch instruction and the target instruction. 
   
     
     
         2 . The processor of  claim 1 , wherein the one or more interceding instructions and the target instruction are executed before the one or more interceding instructions are invalidated. 
     
     
         3 . The processor of  claim 2 , wherein invalidating the one or more interceding instructions causes results of the one or more interceding instructions to be discarded. 
     
     
         4 . The processor of  claim 1 , wherein the one or more interceding instructions are issued only if a number of instructions between the branch instruction and the target instruction is below a threshold number. 
     
     
         5 . The processor of  claim 1 , wherein the branch instruction, the one or more interceding instructions, and the target instruction are executed in a single thread of execution. 
     
     
         6 . The processor of  claim 1 , wherein an outcome of the target instruction and outcomes of one or more instructions succeeding the target instruction are independent from an outcome of the one or more interceding instructions. 
     
     
         7 . The processor of  claim 1 , wherein the one or more interceding instructions are issued if either:
 a predictability value for the branch instruction is below a threshold value for predictability; or   a predicted outcome of the branch instruction indicates that the second path will be followed by the branch instruction.   
     
     
         8 . A processor comprising:
 a cache;   one or more execution units; and   circuitry configured to:
 receive a branch instruction from the cache, wherein a first path of the branch instruction branches to a target instruction, and wherein a second path of the branch instruction results in execution of one or more interceding instructions between the branch instruction and the target instruction; 
 before determining an outcome of the branch instruction, issue the one or more interceding instructions and the target instruction to the one or more execution units; 
 execute the branch instruction to determine if the branch instruction follows the first path or the second path; 
 upon determining that the branch instruction follows the first path, invalidate the one or more interceding instructions between the branch instruction and the target instruction; and 
 upon determining that the branch instruction follows the second path, propagate results of the one or more interceding instructions between the branch instruction and the target instruction. 
   
     
     
         9 . The processor of  claim 8 , wherein the one or more interceding instructions and the target instruction are executed before the one or more interceding instructions are invalidated. 
     
     
         10 . The processor of  claim 8 , wherein the one or more interceding instructions are invalidated by clearing one or more validity bits each corresponding to the one or more interceding instructions. 
     
     
         11 . The processor of  claim 10 , wherein invalidating the one or more interceding instructions causes results of the one or more interceding instructions to be discarded. 
     
     
         12 . The processor of  claim 8 , wherein the one or more interceding instructions are issued only if a number of instructions between the branch instruction and the target instruction is below a threshold number of instructions. 
     
     
         13 . The processor of  claim 12 , wherein one of the one or more execution units is configured to simultaneously execute a number of instructions in a pipeline, and wherein the threshold number of instructions is below the number of instructions simultaneously executed in the pipeline. 
     
     
         14 . The processor of  claim 8 , wherein an outcome of the target instruction is independent from an outcome of the one or more interceding instructions. 
     
     
         15 . The processor of  claim 14 , wherein outcomes of one or more instructions succeeding the target instruction are independent from the outcome of the one or more interceding instructions. 
     
     
         16 . The processor of  claim 8 , wherein the one or more interceding instructions are issued if either:
 a predictability value for the branch instruction is below a threshold value for predictability; or   a predicted outcome of the branch instruction indicates that the second path will be followed by the branch instruction.