US2012217634A9PendingUtilityA9

Semiconductor Device and Method of Forming the Device Using Sacrificial Carrier

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Assignee: SHIM IL KWONPriority: Dec 26, 2007Filed: Mar 2, 2011Published: Aug 30, 2012
Est. expiryDec 26, 2027(~1.5 yrs left)· nominal 20-yr term from priority
Inventors:Il Kwon ShimYaojian LinSeng Guan Chow
H10W 74/00H10W 70/63H10W 72/884H10W 74/15H10W 90/754H10W 72/29H10W 72/59H10W 72/9413H10W 72/0198H10W 70/09H10W 70/093H10W 90/724H10W 90/10H10W 72/241H10W 90/734H10P 72/74H10W 74/117H10W 74/019H10W 72/00H05K 1/187H05K 2201/10674H05K 3/205H05K 1/185H05K 3/4644
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Claims

Abstract

A semiconductor device includes a first semiconductor die or component having a plurality of bumps, and a plurality of first and second contact pads. In one embodiment, the first and second contact pads include wettable contact pads. The bumps are mounted directly to a first surface of the first contact pads to align the first semiconductor die or component. An encapsulant is deposited over the first semiconductor die or component. An interconnect structure is formed over the encapsulant and is connected to a second surface of the first and second contact pads opposite the first surface of the first contact pads. A plurality of vias is formed through the encapsulant and extends to a first surface of the second contact pads. A conductive material is deposited in the vias to form a plurality of conductive vias that are aligned by the second contact pads to reduce interconnect pitch.

Claims

exact text as granted — not AI-modified
1 . A semiconductor device, comprising:
 a first semiconductor die or component having a plurality of bumps;   a plurality of first and second contact pads with the bumps mounted directly to a first surface of the first contact pads to align the first semiconductor die or component;   a first encapsulant deposited over the first semiconductor die or component and around the bumps;   an interconnect structure formed over the first encapsulant and connected to a second surface of the first and second contact pads opposite the first surface of the first contact pads;   a plurality of vias formed through the first encapsulant that extends to a first surface of the second contact pads; and   a conductive material deposited in the vias to form a plurality of conductive vias that are aligned by the second contact pads to reduce interconnect pitch.   
     
     
         2 . The semiconductor device of  claim 1 , further including an insulation layer formed over the conductive vias. 
     
     
         3 . The semiconductor device of  claim 1 , wherein the interconnect structure includes:
 a conductive layer electrically connected to the first and second contact pads; and   an insulation layer formed over the conductive layer and including a void to expose the conductive layer.   
     
     
         4 . The semiconductor device of  claim 1 , further including a conductive pillar formed over the second surface of the first and second contact pads. 
     
     
         5 . The semiconductor device of  claim 1 , further including:
 a second semiconductor die or component mounted over the interconnect structure; and   a second encapsulant deposited over the second semiconductor die or component and interconnect structure.   
     
     
         6 . A semiconductor device, comprising:
 a first semiconductor die or component having a plurality of bumps;   a plurality of first and second wettable contact pads with the bumps mounted to a first surface of the first contact pads to align the first semiconductor die or component;   a first encapsulant deposited over the first semiconductor die or component and around the bumps;   an interconnect structure formed over the first encapsulant and connected to a second surface of the first and second wettable contact pads opposite the first surface of the first wettable contact pads;   a plurality of vias formed through the first encapsulant that extends to a first surface of the second wettable contact pads; and   a conductive material deposited in the vias to form a plurality of conductive vias.   
     
     
         7 . The semiconductor device of  claim 6 , further including an insulation layer formed over the conductive vias. 
     
     
         8 . The semiconductor device of  claim 6 , wherein the interconnect structure includes:
 a conductive layer electrically connected to the first and second wettable contact pads; and   an insulation layer formed over the conductive layer and including a void to expose the conductive layer.   
     
     
         9 . The semiconductor device of  claim 6 , further including a conductive pillar formed over the second surface of the first and second wettable contact pads. 
     
     
         10 . The semiconductor device of  claim 6 , further including:
 a second semiconductor die or component mounted over the interconnect structure; and   a second encapsulant deposited over the second semiconductor die or component and interconnect structure.   
     
     
         11 . The semiconductor device of  claim 6 , wherein the first semiconductor die or component is mounted directly to the first surface of the first wettable contact pads with the bumps. 
     
     
         12 . The semiconductor device of  claim 6 , wherein the conductive vias are aligned with respect to the first surface of the second wettable contact pads to reduce interconnect pitch. 
     
     
         13 . A semiconductor device, comprising:
 a first semiconductor die having a plurality of bumps;   a plurality of first and second contact pads with the bumps mounted directly to a first surface of the first contact pads to align the first semiconductor die;   a first encapsulant deposited over the first semiconductor die and around the bumps;   an interconnect structure formed over the first encapsulant and electrically connected to the first and second contact pads; and   a plurality of conductive vias formed through the first encapsulant that extends to the second contact pads.   
     
     
         14 . The semiconductor device of  claim 13 , further including an insulation layer formed over the conductive vias. 
     
     
         15 . The semiconductor device of  claim 13 , wherein the interconnect structure includes:
 a conductive layer electrically connected to the first and second contact pads; and   an insulation layer formed over the conductive layer and including a void to expose the conductive layer.   
     
     
         16 . The semiconductor device of  claim 13 , further including a conductive pillar formed over the first and second contact pads opposite the conductive vias. 
     
     
         17 . The semiconductor device of  claim 13 , further including:
 a second semiconductor die mounted over the interconnect structure; and   a second encapsulant deposited over the second semiconductor die and interconnect structure.   
     
     
         18 . The semiconductor device of  claim 13 , wherein the conductive vias are aligned with respect to the second contact pads to reduce interconnect pitch. 
     
     
         19 . A semiconductor device, comprising:
 a first semiconductor die having a plurality of bumps;   a plurality of first and second contact pads with the bumps mounted over the first contact pads to align the first semiconductor die;   a first encapsulant deposited over the first semiconductor die and around the bumps;   an interconnect structure formed over the first encapsulant and electrically connected to the first and second contact pads; and   a plurality of conductive vias formed through the first encapsulant that aligns with and extends to the second contact pads to reduce interconnect pitch.   
     
     
         20 . The semiconductor device of  claim 19 , further including an insulation layer formed over the conductive vias. 
     
     
         21 . The semiconductor device of  claim 19 , wherein the interconnect structure includes:
 a conductive layer electrically connected to the first and second contact pads; and   an insulation layer formed over the conductive layer and including a void to expose the conductive layer.   
     
     
         22 . The semiconductor device of  claim 19 , further including a conductive pillar formed over the first and second contact pads opposite the bumps. 
     
     
         23 . The semiconductor device of  claim 19 , further including:
 a second semiconductor die mounted over the interconnect structure; and   a second encapsulant deposited over the second semiconductor die and interconnect structure.   
     
     
         24 . The semiconductor device of  claim 19 , wherein the first semiconductor die is mounted directly to the first contact pads with the bumps. 
     
     
         25 . The semiconductor device of  claim 19 , wherein the first and second contact pads include wettable contact pads.

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