Software programmable hardware state machines

Abstract

The present invention provides software programmable hardware state machines to detect a cause of an error in a processor and prevent the error from occurring. A processor core is provided that includes an execution unit, a programmable mask register and a buffer that stores values representing instructions dispatched to the execution unit. The processor core also includes control logic to determine whether there is a match between a sequence in the mask register and a sequence in the buffer and, upon detecting a match, to generate control signals to perform a desired action. The desired action prevents an unwanted change from occurring to the architectural state of the processor. The processor core further comprises a programmable fix register. In an embodiment, the control logic generates the control signals based on control bits stored in the fix register.

1 . A processor, comprising:
 a programmable mask register;   a buffer configured to store values representing a sequence of instructions;   a programmable fix register configured to store control bits; and   control logic configured to determine whether there is a match between a sequence in the programmable mask register and the sequence in the buffer and, upon detecting a match, to generate control signals based on the control bits in the programmable fix register, to perform a desired action.   
     
     
         2 . The processor core of  claim 1 , wherein the control signals prevent an unwanted change in the architectural state of the processor core. 
     
     
         3 . The processor core of  claim 1 , wherein the control signals stall dispatch of a next instruction to the execution unit. 
     
     
         4 . The processor core of  claim 1 , wherein the control signals insert at least one bubble in a pipeline of the processor. 
     
     
         5 . The processor core of  claim 1 , wherein the control signals generate an exception. 
     
     
         6 . The processor core of  claim 1 , wherein the control signals flush at least a portion of a pipeline of the processor. 
     
     
         7 . The processor core of  claim 1 , wherein the control signals delete instructions in the instruction buffer and re-fetch instructions starting from a specified address. 
     
     
         8 . The processor core of  claim 1 , wherein a first value stored in the buffer includes an opcode of an instruction. 
     
     
         9 . The processor core of  claim 1 , wherein a first value stored in the buffer includes an encoded opcode of an instruction. 
     
     
         10 . The processor core of  claim 1 , wherein the buffer stores values representing instructions that are to be dispatched to the execution unit. 
     
     
         11 . The processor core of  claim 1 , further comprising a decoder to decode the instruction and an encoder to selectively encode the bits decoded by the decoder to produce the values stored in the buffer. 
     
     
         12 . A method to detect a sequence of instructions that causes an error in a processor and to implement a solution, the method comprising:
 storing values in a buffer, wherein the values represent a sequence of instructions to be dispatched to an execution unit;   determining whether there is a match between a sequence in a programmable mask register and the sequence in the buffer; and   upon detecting a match, generating control signals based on control bits in a programmable fix register, to perform a desired action.   
     
     
         13 . The method of  claim 12 , wherein the control signals stall dispatch of a next instruction to the execution unit. 
     
     
         14 . The method of  claim 12 , wherein the control signals insert at least one bubble in a pipeline of the processor. 
     
     
         15 . The method of  claim 12 , wherein a first value stored in the buffer includes an encoded opcode of an instruction. 
     
     
         16 . The method of  claim 12 , further comprising decoding an instruction to generated decoded bits and selectively encoding the decoded bits to produce the values stored in the buffer. 
     
     
         17 . The method of  claim 12 , wherein the control signals delete instructions in the instruction buffer and re-fetch instructions starting from a specified address. 
     
     
         18 . A tangible computer readable storage medium comprising a processor embodied in software, the processor comprising:
 a programmable mask register;   a buffer that stores values representing a sequence of instructions;   a programmable fix register configured to store control bits; and   control logic configured to determine whether there is a match between a sequence in the programmable mask register and the sequence in the buffer and, upon detecting a match, to generate control signals based on the control bits in the programmable fix register, to perform a desired action.   
     
     
         19 . The tangible computer readable storage medium of  claim 18 , wherein the control signals prevent an unwanted change in the architectural state of the processor core. 
     
     
         20 . The tangible computer readable storage medium of  claim 18 , wherein the control signals stall dispatch of a next instruction to the execution unit.