Inventor · disambiguated record
Michael Gottlieb Jensen
Also filed as: JENSEN MICHAEL GOTTLIEB
22 granted patents·4 pending applications·402 citations·filing 2000–2012
96Inventor score
Top patents by PatentIndex Score
26 records- 0193US7490230B2Fetch director employing barrel-incrementer-based round-robin apparatus for use in multithreading microprocessorMIPS TECH INC·Filed 2005·Granted Feb 10, 2009·32 cites·37 claims
- 0293US7149878B1Changing instruction set architecture mode by comparison of current instruction execution address with boundary address register valuesMIPS TECH INC·Filed 2000·Granted Dec 12, 2006·85 cites·36 claims
- 0392US7634638B1Instruction encoding for system register bit set and clearMIPS TECH INC·Filed 2002·Granted Dec 15, 2009·61 cites·12 claims
- 0490US7664936B2Prioritizing thread selection partly based on stall likelihood providing status information of instruction operand register usage at pipeline stagesMIPS TECH INC·Filed 2005·Granted Feb 16, 2010·26 cites·72 claims
- 0589US7558939B2Three-tiered translation lookaside buffer hierarchy in a multithreading microprocessorMIPS TECH INC·Filed 2005·Granted Jul 7, 2009·21 cites·77 claims
- 0688US7660969B2Multithreading instruction scheduler employing thread group prioritiesMIPS TECH INC·Filed 2007·Granted Feb 9, 2010·17 cites·58 claims
- 0788US7657891B2Multithreading microprocessor with optimized thread scheduler for increasing pipeline utilization efficiencyMIPS TECH INC·Filed 2005·Granted Feb 2, 2010·18 cites·39 claims
- 0887US7506140B2Return data selector employing barrel-incrementer-based round-robin apparatusMIPS TECH INC·Filed 2005·Granted Mar 17, 2009·18 cites·36 claims
- 0986US7773621B2Transaction selector employing round-robin apparatus supporting dynamic priorities in multi-port switchMIPS TECH INC·Filed 2006·Granted Aug 10, 2010·16 cites·6 claims
- 1086US7657883B2Instruction dispatch scheduler employing round-robin apparatus supporting multiple thread priorities for use in multithreading microprocessorMIPS TECH INC·Filed 2005·Granted Feb 2, 2010·17 cites·24 claims
- 1186US7509447B2Barrel-incrementer-based round-robin apparatus and instruction dispatch scheduler employing same for use in multithreading microprocessorMIPS TECH INC·Filed 2006·Granted Mar 24, 2009·12 cites·33 claims
- 1286US7509480B2Selection of ISA decoding mode for plural instruction sets based upon instruction addressMIPS TECHNOLOGY INC·Filed 2006·Granted Mar 24, 2009·16 cites·15 claims
- 1385US8078840B2Thread instruction fetch based on prioritized selection from plural round-robin outputs for different thread statesBANERJEE SOUMYA·Filed 2008·Granted Dec 13, 2011·16 cites·13 claims
- 1483US7925859B2Three-tiered translation lookaside buffer hierarchy in a multithreading microprocessorMIPS TECH INC·Filed 2009·Granted Apr 12, 2011·10 cites·25 claims
- 1582US7681014B2Multithreading instruction scheduler employing thread group prioritiesMIPS TECH INC·Filed 2005·Granted Mar 16, 2010·11 cites·53 claims
- 1680US7631130B2Barrel-incrementer-based round-robin apparatus and instruction dispatch scheduler employing same for use in multithreading microprocessorMIPS TECH INC·Filed 2005·Granted Dec 8, 2009·7 cites·30 claims
- 1779US8151268B2Multithreading microprocessor with optimized thread scheduler for increasing pipeline utilization efficiencyJONES DARREN M·Filed 2010·Granted Apr 3, 2012·7 cites·16 claims
- 1872US7760748B2Transaction selector employing barrel-incrementer-based round-robin apparatus supporting dynamic priorities in multi-port switchMIPS TECH INC·Filed 2006·Granted Jul 20, 2010·5 cites·5 claims
- 1966US7961745B2Bifurcated transaction selector supporting dynamic priorities in multi-port switchMIPS TECH INC·Filed 2006·Granted Jun 14, 2011·3 cites·11 claims
- 2066US7600100B2Instruction encoding for system register bit set and clearMIPS TECH INC·Filed 2006·Granted Oct 6, 2009·2 cites·20 claims
- 2162US7990989B2Transaction selector employing transaction queue group priorities in multi-port switchMIPS TECH INC·Filed 2006·Granted Aug 2, 2011·2 cites·7 claims
- 2256US2009271592A1Apparatus For Storing Instructions In A Multithreading MicroprocessorMIPS TECH INC·Filed 2009·Application pending·0 cites
- 2355US2009249351A1Round-Robin Apparatus and Instruction Dispatch Scheduler Employing Same For Use In Multithreading MicroprocessorMIPS TECH INC·Filed 2009·Application pending·0 cites
- 2449US8151093B2Software programmable hardware state machinesBANERJEE SOUMYA·Filed 2006·Granted Apr 3, 2012·0 cites·24 claims
- 2548US2012221838A1Software programmable hardware state machinesBANERJEE SOUMYA·Filed 2012·Application pending·0 cites
- 2645US2008177990A1Synthesized assertions in a self-correcting processor and applications thereofMIPS TECH INC·Filed 2007·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →