Redistributed chip packaging with thermal contact to device backside

Abstract

An integrated circuit assembly includes a panel including an semiconductor device at least partially surrounded by an encapsulant. A panel upper surface and a device active surface are substantially coplanar. The assembly further includes one or more interconnect layers overlying the panel upper surface. Each of the interconnect layers includes an insulating film having contacts formed therein an interconnect metallization formed thereon. A lower surface of the panel is substantially coplanar with either a backside of the device or a lower surface of a thermally and electrically conductive slab that has an upper surface in thermal contact with the device backside. The assembly may also include a set of panel vias. The panel vias are thermally and electrically conductive conduits extending through the panel between the interconnect layer and suitable for bonding with a land grid array (LGA) or other contact structure of an underlying circuit board.

1 .- 8 . (canceled) 
     
     
         9 . An integrated circuit assembly method, comprising:
 forming a panel by forming an encapsulant at least partially surrounding a device, wherein an upper surface of the panel is substantially coplanar with an active surface of the device;   forming a set of panel vias in the panel, the thermal vias extending from an upper surface to a lower surface of the panel, wherein the panel vias comprise an electrically and thermally conductive material; and   forming at least one interconnect layer overlying the panel wherein the interconnect layer includes an insulating film and an interconnect metallization.   
     
     
         10 . The method of  claim 9 , further comprising, prior to forming the panel, removing a portion of a substrate portion of the device to thin the device. 
     
     
         11 . The method of  claim 9 , further comprising, prior to forming the encapsulant, forming a thermal slab in thermal contact with the backside of the device, wherein the thermal slab comprises at least one thermally and electrically conductive metal. 
     
     
         12 . The method of  claim 11 , wherein a lower surface of the panel is substantially coplanar with a lower surface of the thermal slab. 
     
     
         13 . The method of  claim 9 , further comprising:
 prior to forming the encapsulant, affixing the active surface of the device to a carrier plate with an adhesive layer; and   after forming the encapsulant, removing the carrier plate and the adhesive layer.   
     
     
         14 . The method of  claim 9 , further comprising attaching the integrated circuit assembly to a printed circuit board (PCB) wherein the integrated circuit assembly overlies the PCB with the panel lower surface proximal to the PCB and the panel upper surface distal from the PCB. 
     
     
         15 . The method of  claim 14 , wherein the panel lower surface is substantially coplanar with either a backside of the device or a lower surface of a thermally conductive slab having an upper surface in thermal contact with the backside of the device. 
     
     
         16 . The method of  claim 14 , wherein said attaching of the assembly to the PCB includes attaching the panel to land grid array (LGA) pads of the PCB. 
     
     
         17 . The method of  claim 9 , further comprising attaching at least one external device overlying an uppermost interconnect layer. 
     
     
         18 . The method of  claim 9 , further comprising forming a shielding metallization layer overlying an uppermost interconnect layer, wherein the shielding metallization layer comprises a substantially continuous plane of metallization overlying the panel. 
     
     
         19 .- 20 . (canceled)