Integrated circuit chip incorporating a test circuit that allows for on-chip stress testing in order to model or monitor device performance degradation

Abstract

Disclosed is an integrated circuit chip incorporating a test circuit having multiple logic blocks. Each logic block is a matrix of individually selectable, physically different, test devices in a specific class of devices. An embedded processor ensures that specific stress conditions are selectively applied to the test devices and further controls selective testing, by a sensor system, of the test devices to determine the impact of the applied stress conditions. In a laboratory or test system environment, accelerated stress conditions are selectively applied to the test devices and the testing results are used to model device performance degradation due to class-specific failure mechanisms. In the field, stress conditions are selectively applied to test devices so as to mimic stress conditions impacting active devices in use on the same chip and the testing results are used to indirectly monitor performance degradation of the active devices due to class-specific failure mechanisms.

1 . An integrated circuit chip circuit comprising:
 multiple logic blocks, each one of said multiple logic blocks being associated with a specific class of devices and comprising a matrix of individually selectable, physically different, test devices in said specific class;   a sensor system; and   an embedded processor operatively connected to said multiple logic blocks and said sensor system, said embedded processor controlling selective stressing of said test devices by causing a specific test device to be subjected to specific stress conditions and further controlling selective testing of said test devices by causing said sensor system to determine an actual value of a specific electrical characteristic exhibited by said specific test device following application of said specific stress conditions.   
     
     
         2 . The integrated circuit chip of  claim 1 , said sensor system determining different electrical characteristics depending upon said specific class and a specific failure mechanism associated with said specific class. 
     
     
         3 . The integrated circuit chip of  claim 1 ,
 said test devices being duplicates of active devices in any one of the following: a given functional circuit design; and a given semiconductor technology node, and   said testing being performed in order to generate performance degradation models for said active devices.   
     
     
         4 . The integrated circuit chip of  claim 1 , said specific stress conditions comprising a specific voltage and said embedded processor being operatively connected to a voltage regulator and causing said voltage regulator to apply said specific voltage to said test device. 
     
     
         5 . The integrated circuit chip of  claim 1 , said specific stress conditions comprising a specific temperature and said embedded processor being operatively connected to a heat source and causing said heat source to heat said test device to said specific temperature. 
     
     
         6 . The integrated circuit chip of  claim 1 , said embedded processor being in communication with a controller, said controller at least updating embedded processor programming and receiving results of said testing from said embedded processor. 
     
     
         7 . The integrated circuit chip of  claim 6 , said embedded processor further being remote access service (RAS) enabled so as to allow for remote communication between said controller and said embedded processor. 
     
     
         8 . The integrated circuit chip of  claim 1 , said multiple logic blocks each being connected to a corresponding data-in register and a corresponding data-out register, said embedded processor further controlling said testing by transmitting a first enable signal to said corresponding data-in register of a specific logic block containing said specific test device so that data-in is released to said given logic block, causing said specific test device to process said data-in, causing said sensor system to determine said actual value of said specific electrical characteristic and transmitting a second enable signal to said corresponding data-out register of said specific logic block when processing of said data-in by said specific test device is complete so that data-out is released. 
     
     
         9 . An integrated circuit chip incorporated into a test system, said integrated circuit chip comprising:
 at least one functional circuit comprising a plurality of active devices; and   a test circuit comprising:
 multiple logic blocks, each one of said multiple logic blocks being associated with a specific class of devices and comprising a matrix of individually selectable, physically different, test devices in said specific class, said test devices being duplicates of said active devices; 
 a sensor system; and 
 an embedded processor operatively connected to said multiple logic blocks and said sensor system,
 said embedded processor controlling selective stressing of said test devices by causing a specific test device to be subjected to specific stress conditions and further controlling selective testing of said specific test device by causing said sensor system to determine an actual value of a specific electrical characteristic exhibited by said specific test device following application of said specific stress conditions, and 
 said embedded processor further being remote access service (RAS) enabled so as to allow for remote communication with said embedded processor. 
 
   
     
     
         10 . The integrated circuit chip of  claim 9 , said sensor system determining different electrical characteristics depending upon said specific class and a specific failure mechanism associated with said specific class. 
     
     
         11 . The integrated circuit chip of  claim 9 , said testing being performed in order to generate performance degradation models for said active devices. 
     
     
         12 . The integrated circuit chip of  claim 9 , said specific stress conditions comprising a specific voltage and said embedded processor being operatively connected to a voltage regulation system for said test system and causing said voltage regulation system to apply said specific voltage to said specific test device. 
     
     
         13 . The integrated circuit chip of  claim 10 , said specific stress conditions comprising a specific temperature and said embedded processor regulating an amount of processing performed by said test system so as to heat said specific test device to said specific temperature. 
     
     
         14 . The integrated circuit of  claim 10 , said multiple logic blocks each being connected to a corresponding data-in register and a corresponding data-out register, said embedded processor further controlling said testing by transmitting a first enable signal to said corresponding data-in register of a specific logic block containing said specific test device so that data-in is released to said given logic block, causing said specific test device to process said data-in, causing said sensor system to determine said actual value of said specific electrical characteristic and transmitting a second enable signal to said corresponding data-out register of said specific logic block when processing of said data-in by said specific test device is complete so that data-out is released. 
     
     
         15 . An integrated circuit chip incorporated into a product, said integrated circuit chip comprising:
 at least one functional circuit comprising a plurality of active devices in use in said product; and   a test circuit comprising:
 multiple logic blocks, each one of said multiple logic blocks being associated with a specific class of devices and comprising a matrix of individually selectable, physically different, test devices in said specific class, said test devices being duplicates of said active devices; 
 a sensor system; and 
 an embedded processor operatively connected to said multiple logic blocks and said sensor system,
 said embedded processor controlling selective stressing of said test devices by causing a specific test device to be subjected to specific stress conditions and further controlling selective testing of said test devices by causing said sensor system to determine an actual value of a specific electrical characteristic exhibited by said specific test device following application of said specific stress conditions, said specific stress conditions approximating in-use stress conditions imparted on a corresponding active device, and 
 said embedded processor further being remote access service (RAS) enabled so as to allow for remote communication with said embedded processor. 
 
   
     
     
         16 . The integrated circuit chip of  claim 15 , said sensor system determining different electrical characteristics depending upon said specific class and a specific failure mechanism associated with said specific class. 
     
     
         17 . The integrated circuit chip of  claim 15 , said testing being performed in order to monitor said performance degradation of said test devices and, thereby, to monitor said performance degradation of said active devices. 
     
     
         18 . The integrated circuit chip of  claim 15 , said embedded processor further comparing said actual value with a predicted value for said specific electrical characteristic as indicated by a performance degradation model. 
     
     
         19 . The integrated circuit chip of  claim 18 , said embedded processor updating said performance degradation model when said actual value and said predicted value are different. 
     
     
         20 . The integrated circuit chip of  claim 15 , said specific stress conditions comprising a specific voltage and said embedded processor being operatively connected to a voltage regulation system for said product and causing said voltage regulation system to apply said specific voltage to said specific test device.