Data retention structure for non-volatile memory

Abstract

A data retention structure in a memory element that stores data as a plurality of conductivity profiles is disclosed. The memory element can be used in a variety of electrical systems and includes a conductive oxide layer, an ion impeding layer, and an electrolytic tunnel barrier layer. A write voltage applied across the memory element causes a portion of the mobile ions to move from the conductive oxide layer, through the ion impeding layer, and into the electrolytic tunnel barrier layer thereby changing a conductivity of the memory element, or the write voltage causes a quantity of the mobile ions to move from the electrolytic tunnel barrier layer, through the ion impeding layer, and back into the conductive oxide layer. The ion impeding layer is operative to substantially stop mobile ion movement when a voltage that is less than the write voltage is applied across the memory element.

1 . A non-volatile memory device, comprising:
 a memory element (ME) having exactly two terminals, the ME including electrically in series with the two terminals
 a conductive oxide layer including mobile ions, 
 an ion impeding layer, and 
 an electrolytic tunnel barrier layer, 
   the ME is reversibly switchable between different conductivity profiles by applying different write voltages across the two terminals, and   the ion impeding layer operative to substantially stop mobile ion movement between the electrolytic tunnel barrier layer and the conductive oxide layer when voltages other than the different write voltages are applied across the two terminals.   
     
     
         2 . The non-volatile memory device as set forth in  claim 1 , wherein the different conductivity profiles of the ME are non-destructively determined by applying a read voltage across the two terminals. 
     
     
         3 . The non-volatile memory device as set forth in  claim 1 , wherein the ion impeding layer is operative to substantially stop ion movement when a read voltage is applied across the two terminals. 
     
     
         4 . The non-volatile memory device as set forth in  claim 1  and further comprising:
 a non-ohmic device sandwiched between a pair of electrodes, the non-ohmic device is electrically in series with the two terminals and with the pair of electrodes. 
 
     
     
         5 . The non-volatile memory device as set forth in  claim 1 , wherein the conductive oxide layer comprises a conductive perovskite. 
     
     
         6 . The non-volatile memory device as set forth in  claim 5 , wherein the conductive perovskite is a material selected from the group consisting of PCMO, LSCO, LNO, LCMO, PMO, LSMO, strontium titanate (STO), and a reduced STO. 
     
     
         7 . The non-volatile memory device as set forth in  claim 1 , wherein the electrolytic tunnel barrier layer has a first conductivity and the ion impeding layer has a second conductivity that is higher than the first conductivity. 
     
     
         8 . The non-volatile memory device as set forth in  claim 1 , wherein current flow through the ME is a non-linear function of a voltage applied across the two terminals. 
     
     
         9 . The non-volatile memory device as set forth in  claim 8 , wherein the ME includes a non-linear I-V curve. 
     
     
         10 . The non-volatile memory device as set forth in  claim 1 , wherein the mobile ions comprise mobile oxygen ions. 
     
     
         11 . The non-volatile memory device as set forth in  claim 1 , wherein the ion impeding layer is made from a material selected from the group consisting of LaAlO 3 , TiO x , TaO x , AlO x , SiO x , IrO x , MgO, Pt, strontium ruthenate (SRO), and a reduced SRO. 
     
     
         12 . The non-volatile memory device as set forth in  claim 1 , wherein the electrolytic tunnel barrier layer is made from an electronically insulating material. 
     
     
         13 . The non-volatile memory device as set forth in  claim 12 , wherein the electronically insulating material is a material selected from the group consisting of yttria-stabilized zirconia (YSZ), ZrO 2 , HfO 2 , and Er 2 O 3 . 
     
     
         14 . The non-volatile memory device as set forth in  claim 1 , wherein a conductivity profile of the ME is indicative of at least one bit of stored data that is retained in an absence of electrical power. 
     
     
         15 . An electrical system, comprising:
 a bus;   a processing unit in electrical communication with the bus;   an input/output (I/O) unit in electrical communication with the bus; and   a memory unit in electrical communication with the processing unit, the memory unit including
 a substrate including active circuitry, 
 a plurality of first conductive array lines, 
 a plurality of second conductive array lines, and 
 a plurality of memory cells, each memory cell including a first terminal in electrical communication with only one of the plurality of first conductive array lines and a second terminal in electrical communication with only one of the plurality of second conductive array lines, the plurality of memory cells and the plurality of first and second conductive array lines are positioned over the substrate with the plurality of first and second conductive array lines in electrical communication with at least a portion of the active circuitry, the portion configured for data operations on the memory cells, 
 each memory cell including a memory element (ME) electrically in series with its respective first and second terminals, each ME having exactly two electrodes, current flow through the ME is a non-linear function of a voltage applied across the two electrodes, the ME including electrically in series with its two electrodes
 a conductive oxide layer including mobile ions, 
 an ion impeding layer, and 
 an electrolytic tunnel barrier layer. 
 
   
     
     
         16 . The electrical system of  claim 15 , wherein the memory unit includes a plurality of stacked non-volatile two-terminal cross-point memory arrays. 
     
     
         17 . A non-volatile memory element, comprising:
 a first terminal;   a second terminal;   a conductive oxide layer including mobile ions;   an electrolytic tunnel barrier layer having a first thickness that is approximately 50 Å or less, the electrolytic tunnel barrier layer is permeable to the mobile ions when a write voltage is applied across the first and second terminals; and   an ion impeding layer configured to substantially stop mobile ion movement between the conductive oxide layer and the electrolytic tunnel barrier layer for voltages other than the write voltage that are applied across the first and second terminals, and   wherein the conductive oxide layer, the ion impeding layer, and the electrolytic tunnel barrier layer are electrically in series with the first and second terminals.   
     
     
         18 . The non-volatile memory element as set forth in  claim 17 , wherein the conductive oxide layer comprises a conductive perovskite. 
     
     
         19 . The non-volatile memory element as set forth in  claim 18 , wherein the conductive perovskite is a material selected from the group consisting of PCMO, LSCO, LNO, LCMO, PMO, LSMO, strontium titanate (STO), and a reduced STO. 
     
     
         20 . The non-volatile memory element as set forth in  claim 17 , wherein the ion impeding layer is made from a material selected from the group consisting of LaAlO 3 , TiO x , TaO x , AlO x , SiO x , IrO x , MgO, Pt, strontium ruthenate (SRO), and a reduced SRO. 
     
     
         21 . The non-volatile memory element as set forth in  claim 17 , wherein current flow through the ME is a non-linear function of a voltage applied across the first and second terminals. 
     
     
         22 . The non-volatile memory element as set forth in  claim 17 , wherein the electrolytic tunnel barrier layer is made from an electronically insulating material selected from the group consisting of yttria-stabilized zirconia (YSZ), ZrO 2 , HfO 2 , and Er 2 O 3 . 
     
     
         23 . An electrical system, comprising:
 a bus;   a processing unit in electrical communication with the bus;   an input/output (I/O) unit in electrical communication with the bus; and   a storage unit in electrical communication with the bus, the storage unit including
 a substrate including active circuitry, 
 a plurality of first conductive array lines, 
 a plurality of second conductive array lines, and 
 a plurality of memory cells, each memory cell including a first terminal in electrical communication with only one of the plurality of first conductive array lines and a second terminal in electrical communication with only one of the plurality of second conductive array lines, the plurality of memory cells and the plurality of first and second conductive array lines are positioned over the substrate with the plurality of first and second conductive array lines in electrical communication with at least a portion of the active circuitry, the portion configured for data operations on the memory cells, 
 each memory cell including a memory element (ME) electrically in series with its respective first and second terminals, each ME having exactly two electrodes and including electrically in series with its two electrodes
 a conductive oxide layer including mobile ions; 
 an electrolytic tunnel barrier layer that is permeable to the mobile ions when a write voltage is applied across the first and second terminals; and 
 an ion impeding layer configured to substantially stop mobile ion movement between the conductive oxide layer and the electrolytic tunnel barrier layer for voltages other than the write voltage that are applied across the first and second terminals. 
 
   
     
     
         24 . A non-volatile memory device, comprising:
 a substrate including active circuitry;   a plurality of first conductive array lines;   a plurality of second conductive array lines; and   a plurality of memory cells, each memory cell including a first terminal in electrical communication with only one of the plurality of first conductive array lines and a second terminal in electrical communication with only one of the plurality of second conductive array lines, the plurality of memory cells and the plurality of first and second conductive array lines are positioned over the substrate with the plurality of first and second conductive array lines in electrical communication with at least a portion of the active circuitry, the portion configured for data operations on the memory cells,   each memory cell including a memory element (ME) electrically in series with its respective first and second terminals, each ME having exactly two electrodes and including electrically in series with its two electrodes
 a conductive oxide layer including mobile ions; 
 an electrolytic tunnel barrier layer that is permeable to the mobile ions when a write voltage is applied across the first and second terminals; and 
 an ion impeding layer configured to substantially stop mobile ion movement between the conductive oxide layer and the electrolytic tunnel barrier layer for voltages other than the write voltage that are applied across the first and second terminals. 
   
     
     
         25 . The non-volatile memory device as set forth in  claim 24 , wherein the electrolytic tunnel barrier layer has a first thickness that is approximately 50 Å or less. 
     
     
         26 . The non-volatile memory device as set forth in  claim 25 , wherein current flow through the ME is a non-linear function of a voltage applied across the two electrodes. 
     
     
         27 . The non-volatile memory device as set forth in  claim 24 , wherein the ion impeding layer is made from a material selected from the group consisting of LaAlO 3 , TiO x , TaO x , AlO x , SiO x , IrO x , MgO, Pt, strontium ruthenate (SRO), and a reduced SRO. 
     
     
         28 . The non-volatile memory device as set forth in  claim 24 , wherein the plurality of first conductive array lines have an orientation that is substantially orthogonal to the plurality of second conductive array lines and each memory cell is positioned substantially between an intersection of one of the plurality of first conductive array lines with one of the plurality of second conductive array lines.