Structures and methods for reducing dopant out-diffusion from implant regions in power devices

Abstract

In accordance with an embodiment, a method of forming a semiconductor structure can include forming a source region of a first conductivity type in a well region of a second conductivity type within a semiconductor region, and forming a first diffusion barrier region disposed between the source region and the well region. The method can include forming a heavy body region of the second conductivity type in the well region and forming a second diffusion bather region having a portion on a side of the heavy body region with a thickness different than a thickness of a portion on a bottom portion of the heavy body region. The method can also include forming a gate electrode, and forming a dielectric insulating the gate electrode from the semiconductor region.

1 . A method of forming a semiconductor structure, comprising:
 forming a source region of a first conductivity type in a well region of a second conductivity type within a semiconductor region;   forming a first diffusion barrier region disposed between the source region and the well region;   forming a heavy body region of the second conductivity type in the well region;   forming a second diffusion barrier region having a portion on a side of the heavy body region with a thickness different than a thickness of a portion on a bottom portion of the heavy body region;   forming a gate electrode; and   forming a dielectric insulating the gate electrode from the semiconductor region.   
     
     
         2 . The method of  claim 1 , wherein the heavy body region has a higher doping concentration than the well region. 
     
     
         3 . The method of  claim 1 , further comprising:
 forming a drift region of the first conductivity type in the semiconductor region, well region being disposed over the drift region   
     
     
         4 . The method of  claim 1 , wherein at least one of the first diffusion barrier region or the second diffusion barrier region includes carbon. 
     
     
         5 . The method of  claim 1 , further comprising:
 forming a trench extending into the semiconductor region, the gate electrode being disposed in the trench, the gate dielectric extending along a sidewall and a bottom of the trench, the well region and the source region are in contact with the sidewall of the trench.   
     
     
         6 . The method of  claim 1 , wherein the gate electrode has a depth in the semiconductor region greater than a depth of the source region in the semiconductor region. 
     
     
         7 . The method of  claim 1 , wherein the gate electrode has a depth in the semiconductor region greater than a depth of the well region in the semiconductor region. 
     
     
         8 . The method of  claim 1 , wherein the first diffusion barrier region at least partially overlaps with the source region. 
     
     
         9 . A method of forming a semiconductor structure, comprising:
 forming a well region of a first conductivity type in a semiconductor region;   forming a source region of a second conductivity type in the well region;   forming a heavy body region of the first conductivity type in the well region, the heavy body region having a higher doping concentration than the well region;   forming a diffusion barrier region in the well region at least partially surrounding the heavy body region;   forming a gate electrode; and   forming a gate dielectric disposed between the gate electrode and the semiconductor region.   
     
     
         10 . The method of  claim 9 , wherein the diffusion barrier region includes carbon. 
     
     
         11 . The method of  claim 9 , further comprising:
 forming a trench extending into the semiconductor region, the gate electrode being disposed in the trench, the gate dielectric extending along a sidewall and a bottom of the trench, the well region and the source region are in contact with the sidewall of the trench.   
     
     
         12 . The method of  claim 9 , wherein the gate electrode has a depth in the semiconductor region greater than a depth of the source region in the semiconductor region. 
     
     
         13 . The method of  claim 9 , wherein the diffusion barrier region at least partially overlaps with the heavy body region. 
     
     
         14 . The method of  claim 9 , wherein the diffusion barrier region extends along a side and a bottom of the heavy body region. 
     
     
         15 . The method of  claim 9 , wherein the diffusion barrier region has a portion on a side of the heavy body region with a thickness different than a thickness of a portion on a bottom portion of the heavy body region. 
     
     
         16 . The method of  claim 9 , wherein the diffusion barrier region is a first diffusion barrier region,
 the method further comprising:   forming a second diffusion bather region disposed between the source region and the well region.   
     
     
         17 . A method of forming a semiconductor structure, comprising:
 forming a source region of a first conductivity type in a well region of a second conductivity type;   forming a first diffusion barrier region aligned along a first axis and disposed between the source region and the well region;   forming a heavy body region of the second conductivity type in the well region;   forming a second diffusion barrier region having a portion aligned along a second axis substantially perpendicular to the first axis;   forming a gate electrode; and   forming a gate dielectric insulating the gate electrode from the semiconductor region.   
     
     
         18 . The method of  claim 17 , wherein the heavy body region has a higher doping concentration than the well region. 
     
     
         19 . The method of  claim 17 , wherein the portion of the second diffusion barrier has a thickness different than a thickness of the portion of the first diffusion barrier region. 
     
     
         20 . The method of  claim 17 , wherein the portion of the second diffusion barrier region is a first portion of the second diffusion barrier region, the second diffusion barrier region has a second portion aligned along a third axis substantially parallel to the first axis. 
     
     
         21 . A semiconductor structure, comprising:
 a source region of a first conductivity type in a well region of a second conductivity type within a semiconductor region;   a first diffusion barrier region disposed between the source region and the well region;   a heavy body region of the second conductivity type in the well region;   a second diffusion barrier region having a portion on a side of the heavy body region with a thickness different than a thickness of a portion on a bottom portion of the heavy body region;   a gate electrode; and   a dielectric insulating the gate electrode from the semiconductor region.