Structure for use in fabrication of pin heterojunction tfet

Abstract

A structure for use in fabrication of a PiN heterojunction tunnel field effect transistor (TFET) includes a silicon wafer comprising an alignment trench, a p-type silicon germanium (SiGe) region, and a hydrogen implantation region underneath the p-type SiGe region and the alignment trench that divides the silicon wafer into a upper silicon region and a lower silicon region, wherein the upper silicon region comprises the alignment trench and the p-type SiGe region; and a first oxide layer located over the alignment trench and the p-type SiGe region that fills the alignment trench and is bonded to a second oxide layer located on a handle wafer; wherein the alignment trench is configured to align a wiring level of the device comprising the PiN heterojunction TFET to the p-type SiGe region.

1 . A structure for use in fabrication of a PiN heterojunction tunnel field effect transistor (TFET), the structure comprising:
 a silicon wafer, the silicon wafer comprising an alignment trench and a p-type silicon germanium (SiGe) region, wherein the silicon wafer further comprises a hydrogen implantation region in the silicon wafer underneath the p-type SiGe region and the alignment trench, the hydrogen implantation region dividing the silicon wafer into a upper silicon region and a lower silicon region, and wherein the upper silicon region comprises the alignment trench and the p-type SiGe region; and   a first oxide layer located over the alignment trench and the p-type SiGe region in the silicon wafer, wherein the oxide layer fills the alignment trench, and wherein the first oxide layer is bonded to a second oxide layer located on a handle wafer, wherein the first oxide layer and the second oxide layer comprise a bonded oxide layer;   wherein the alignment trench is configured to align a wiring level of the device comprising the PiN heterojunction TFET to the p-type SiGe region during formation of the device comprising the PiN heterojunction TFET.   
     
     
         2 . The structure of  claim 1 , wherein the p-type SiGe region comprises in-situ boron-doped SiGe, and wherein the depth of the p-type SiGe region is about 50 nm or less. 
     
     
         3 . The structure of  claim 1 , wherein the thickness of the silicon layer is between about 10 nm and about 50 nm. 
     
     
         4 . The structure of  claim 1 , wherein the thickness of the oxide layer is between about 50 nm and about 400 nm. 
     
     
         5 . The structure of  claim 1 , further comprising a PiN heterojunction that comprises a p-type region, the p-type region comprising the p-type SiGe region. 
     
     
         6 . The structure of  claim 5 , further comprising a TFET, the TFET comprising a tunnel barrier, the tunnel barrier comprising the PiN heterojunction. 
     
     
         7 . The structure of  claim 1 , wherein the handle wafer comprises the second oxide layer and a bulk silicon layer. 
     
     
         8 . The structure of  claim 1 , wherein the thickness of the bonded oxide layer is between about 50 nm and about 400 nm