Vertical junction field effect transistor with mesa termination and method of making the same

Abstract

A vertical junction field effect transistor (VJFET) having a mesa termination and a method of making the device are described. The device includes: an n-type mesa on an n-type substrate; a plurality of raised n-type regions on the mesa comprising an upper n-type layer on a lower n-type layer; p-type regions between and adjacent the raised n-type regions and along a lower sidewall portion of the raised regions; dielectric material on the sidewalls of the raised regions, on the p-type regions and on the sidewalls of the mesa; and electrical contacts to the substrate (drain), p-type regions (gate) and the upper n-type layer (source). The device can be made in a wide-bandgap semiconductor material such as SiC. The method includes selectively etching through an n-type layer using a mask to form the raised regions and implanting p-type dopants into exposed surfaces of an underlying n-type layer using the mask.

1 .- 15 . (canceled) 
     
     
         16 . A method of making a semiconductor device comprising:
 selectively etching through a first layer of n-type semiconductor material through openings in a mask to form raised regions and to expose an underlying second layer of n-type semiconductor material, wherein the second layer of n-type semiconductor material is on a third layer of n-type semiconductor material which is on an n-type substrate;   implanting p-type dopants into exposed surfaces of the second layer of n-type semiconductor material through openings in the mask to form implanted p-type regions;   removing the mask;   selectively etching through the third layer of n-type semiconductor material in a peripheral region of the device to expose underlying n-type substrate and to form a mesa having sidewalls and an upper surface, wherein the raised regions and the implanted p-type regions are on the upper surface of the mesa;   forming a first dielectric layer on the sidewalls of the mesa, on exposed surfaces of the substrate adjacent the mesa sidewalls, on the implanted p-type regions on the upper surface of the mesa and on the sidewalls and upper surfaces of the raised regions;   selectively etching the dielectric layer to expose the upper surfaces of the raised regions and at least a portion of the implanted p-type region on the upper surface of the mesa adjacent the raised regions;   forming source ohmic contacts on the exposed upper surfaces of the raised regions;   forming a gate ohmic contact on the exposed implanted p-type region on the upper surface of the mesa;   forming a drain ohmic contact on the n-type substrate opposite the third layer of n-type semiconductor material;   forming one or more additional dielectric layers between and adjacent the raised regions on the upper surface of the mesa, on the mesa sidewalls and on the substrate adjacent the mesa;   selectively etching through the one or more additional dielectric layers to expose the source ohmic contacts and the gate ohmic contact;   forming one or more metal layers on the source ohmic contacts;   forming one or more metal layers on the gate ohmic contact; and   forming one or more metal layers on the drain ohmic contact.   
     
     
         17 . The method of  claim 16 , wherein the n-type substrate, the first layer of n-type semiconductor material, the second layer of n-type semiconductor material and the third layer of n-type semiconductor material each comprise a wide-bandgap semiconductor material. 
     
     
         18 . The method of  claim 16 , wherein the n-type substrate, the first layer of n-type semiconductor material, the second layer of n-type semiconductor material and the third layer of n-type semiconductor material each comprise SiC. 
     
     
         19 . The method of  claim 16 , wherein the mask comprises an etch mask layer and an implantation mask layer and wherein the implantation mask layer is on the first layer of n-type semiconductor material. 
     
     
         20 . The method of  claim 19 , wherein the etch mask layer comprises Ni and has a thickness of greater than 500 Angstroms. 
     
     
         21 . The method of  claim 19 , wherein the implantation mask layer comprises SiO 2  and has a thickness of greater than 1.5 μm. 
     
     
         22 . The method of  claim 19 , wherein the etch mask layer comprises Ni and the implantation mask layer comprises SiO 2 . 
     
     
         23 . The method of  claim 16 , wherein the second layer of n-type semiconductor material is partially etched into during the etching. 
     
     
         24 . The method of  claim 16 , wherein the first dielectric layer comprises SiO 2 . 
     
     
         25 . The method of  claim 16 , further comprising:
 epitaxially growing the third layer of n-type semiconductor material on the n-type substrate;   epitaxially growing the second layer of n-type semiconductor material on the third layer of n-type semiconductor material; and   epitaxially growing the first layer of n-type semiconductor material on the second layer of n-type semiconductor material;   before selectively etching through a first layer of n-type semiconductor material.   
     
     
         26 . The method of  claim 16 , further comprising:
 epitaxially growing the third layer of n-type semiconductor material on the n-type substrate;   epitaxially growing the second layer of n-type semiconductor material on the third layer of n-type semiconductor material; and   implanting n-type dopants in the second layer of n-type semiconductor material to form the third layer of n-type semiconductor material;   before selectively etching through the first layer of n-type semiconductor material.   
     
     
         27 . The method of  claim 16 , further comprising:
 forming an implantation mask layer comprising SiO 2  on the third layer of n-type semiconductor material;   selectively etching through the implantation mask layer to form openings therein; and   selectively forming an etch mask layer comprising Ni on the selectively etched implantation mask layer to form the mask;   before selectively etching through the first layer of n-type semiconductor material.   
     
     
         28 . The method of  claim 27 , wherein the implantation mask layer is formed by plasma enhanced chemical vapor deposition (PECVD).