Qfn package and manufacturing process thereof

Abstract

The present invention provides a Quad Flat Non-leaded (QFN) package, which comprises a chip, a lead frame, a plurality of composite bumps and an encapsulant. The chip has a plurality of pads, and the lead frame has a plurality of leads. Each of the plurality of composite bumps has a first conductive layer and a second conductive layer. The first conductive layer is electrically connected between one of the pads and the second conductive layer, and the second conductive layer is electrically connected between the first conductive layer and one of the leads. The encapsulant encapsulates the chip, the leads and the composite bumps. Thereby, a QFN package with composite bumps and a semi-cured encapsulant is forming between the spaces of leads of lead frame before chip bonded to the lead frame are provided.

1 . A Quad Flat Non-leaded (QFN) package, comprising:
 a chip;   a lead frame, having a plurality of leads;   a plurality of composite bumps, each having a first conductive layer and a second conductive layer, the first conductive layer being electrically connected between the chip and the second conductive layer, and the second conductive layer being electrically connected between the first conductive layer and one of the leads; and   an encapsulant, encapsulating the chip, the leads and the composite bumps, and an encapsulation interface which is not higher than a top surface of the lead frame.   
     
     
         2 . The QFN package as claimed in  claim 1 , further comprising a plurality of plated structures, one of which is adhered between the second conductive layer and the lead. 
     
     
         3 . The QFN package as claimed in  claim 2 , wherein each of the plated structures is one of solder and a copper pillar with a solder cap. 
     
     
         4 . The QFN package as claimed in  claim 1 , further comprising a covering third conductive layer, which covers surfaces of the composite bumps. 
     
     
         5 . The QFN package as claimed in  claim 1 , wherein the chip having a redistribution layer (RDL) to electrically connect to the first conductive layer of each of the composite bumps. 
     
     
         6 . The QFN package as claimed in  claim 1 , further comprising a plurality of conductive paste, respectively disposed between and adhering each of the composite bumps and a corresponding lead of the leads. 
     
     
         7 . The QFN package as claimed in  claim 1 , wherein the encapsulant is thermosetting resin. 
     
     
         8 . The QFN package as claimed in  claim 1 , wherein the first conductive layer is made of a material selected from copper, nickel, aluminum, zinc, and combinations thereof. 
     
     
         9 . The QFN package as claimed in  claim 1 , wherein the second conductive layer is made of a material selected from gold, copper, silver, tin, zinc, indium, and combinations thereof. 
     
     
         10 . A manufacturing process for Quad Flat Non-leaded (QFN) packages, comprising the steps of:
 forming a semi-cured encapsulant between a plurality of leads of a matrix lead frame on a bottom support carrier;   bonding a plurality chips on the leads of the matrix lead frame, each of the chips being electrically connected to a part of the leads of the matrix lead frame by a plurality of bumps after the semi-cured encapsulant is fully cured;   encapsulating the chips and the matrix lead frame; and   forming a QFN package by singulating the encapsulated chips and the encapsulated matrix lead frame, wherein the QFN package comprises one of the encapsulated chips and a part of the encapsulated matrix lead frame.   
     
     
         11 . The manufacturing process as claimed in  claim 10 , wherein the semi-cured encapsulant is not higher than a top surface of the leads of the matrix lead frame. 
     
     
         12 . The manufacturing process as claimed in  claim 10 , wherein each of the leads has an inner lead portion and an outer lead portion, and a bottom surface of the inner lead portion of each of the leads is higher than a bottom surface of the outer lead portion of each of the leads. 
     
     
         13 . The manufacturing process as claimed in  claim 10 , wherein each of the bumps is a composite bump, including a first conductive layer and a second conductive layer, which is softer than the first conductive layer. 
     
     
         14 . The manufacturing process as claimed in  claim 12 , wherein each of the chips is electrically connected to a top surface of the inner lead portions of the part of the leads of the matrix lead frame. 
     
     
         15 . The manufacturing process as claimed in  claim 10 , wherein the plurality of bumps are directly connected to the leads of the matrix lead frame by thermo-ultrasonic bonding.