Transistor with buried silicon germanium for improved proximity control and optimized recess shape

Abstract

A method of forming a semiconductor device that includes providing a substrate including a semiconductor layer on a germanium-containing silicon layer and forming a gate structure on a surface of a channel portion of the semiconductor layer. Well trenches are etched into the semiconductor layer on opposing sides of the gate structure. The etch process for forming the well trenches forms an undercut region extending under the gate structure and is selective to the germanium-containing silicon layer. Stress inducing semiconductor material is epitaxially grown to fill at least a portion of the well trench to provide at least one of a stress inducing source region and a stress inducing drain region having a planar base.

1 . A semiconductor device comprising:
 a substrate comprised of a semiconductor layer and germanium-containing silicon layer, wherein the semiconductor layer provides a channel portion of the semiconductor device;   a gate structure present on the channel portion of the semiconductor layer; and   stress inducing source and drain regions doped on opposing sides of the channel portion of the semiconductor layer, wherein the stress inducing source and drain regions include an undercut portion that extends under the gate structure and the stress inducing source and drain regions have a planar base defined by the germanium-containing silicon layer.   
     
     
         2 . The semiconductor device of  claim 1 , wherein the semiconductor layer is composed of greater than 90% silicon and has a (100) orientation, and the germanium-containing silicon layer comprises greater than 50% germanium. 
     
     
         3 . The semiconductor device of  claim 1 , wherein the undercut portion of the stress inducing source and drain regions comprise a sidewall defined by (111) facets intersecting at an apex that is underlying the gate structure. 
     
     
         4 . The semiconductor device of  claim 1 , wherein the undercut portion of the stress inducing source and drain regions comprise a sidewall that is perpendicular to an upper surface of the semiconductor layer. 
     
     
         5 . The semiconductor device of  claim 1 , wherein the stress inducing source and drain regions are comprised of p-type silicon germanium (SiGe), or the stress inducing source and drain regions are comprised of n-type silicon doped with carbon (Si:C).