Method for fabricating nonvolatile memory device

Abstract

Provided are a nonvolatile memory device and a method for fabricating the same. The nonvolatile memory device may include a stacked structure, a semiconductor pattern, an information storage layer, and a fixed charge layer. The stacked structure may be disposed over a semiconductor substrate. The stacked structure may include conductive patterns and interlayer dielectric patterns alternately stacked therein. The semiconductor pattern may be connected to the semiconductor substrate by passing through the stacked structure. The information storage layer may be disposed between the semiconductor pattern and the conductive patterns. The fixed charge layer may be disposed between the semiconductor pattern and the interlayer dielectric pattern. The fixed charge layer may include fixed charges. Electrical polarity of the fixed charges may be equal to electrical polarity of majority carriers of the semiconductor pattern.

1 .- 10 . (canceled) 
     
     
         11 . A method for fabricating a nonvolatile memory device, comprising:
 alternately stacking a plurality of first material layers and a plurality of second material layers on a semiconductor substrate;   forming first openings passing through the first and second material layers and exposing the semiconductor substrate;   forming a fixed charge layer on an inner wall of the first openings, the fixed charge layer being adapted to generate fixed charges;   forming semiconductor patterns in the first openings, the semiconductor patterns extending from the semiconductor substrate to contact the fixed charge layer;   forming a second opening passing through the first and second material layers between the first openings;   removing the first material layers and portions of the fixed charge layer contacting the first material layers to form gate regions exposing portions of the semiconductor patterns and interlayer dielectric patterns;   forming a data storage layer contacting the portions of the semiconductor patterns in the gate regions, respectively; and   forming conductive patterns on the data storage layer in the gate regions.   
     
     
         12 . The method as claimed in  claim 11 , wherein the semiconductor pattern includes a p-type semiconductor material, and the fixed charge layer includes elements generating positive fixed charges. 
     
     
         13 . The method as claimed in  claim 12 , wherein the elements generating the positive fixed charges include nitrogen (N), hydrogen (H), hafnium (HF), and/or zirconium (Zr). 
     
     
         14 . The method as claimed in  claim 11 , wherein the semiconductor pattern includes an n-type semiconductor material, and the fixed charge layer includes elements generating negative fixed charges. 
     
     
         15 . The method as claimed in  claim 14 , wherein the elements generating the negative fixed charges include fluorine (F) and/or aluminum (Al). 
     
     
         16 . The method as claimed in  claim 11 , wherein forming the fixed charge layer includes performing a plasma process or an annealing process using a process gas including elements adapted to generate the fixed charges. 
     
     
         17 . The method as claimed in  claim 11 , wherein forming the fixed charge layer includes depositing an insulating layer including the elements adapted to generate the fixed charges. 
     
     
         18 . The method as claimed in  claim 11 , wherein forming the fixed charge layer includes ion-implanting elements generating the fixed charge. 
     
     
         19 . The method as claimed in  claim 11 , wherein forming the data storage layer includes conformally forming the data storage layer along surfaces of the semiconductor patterns and surfaces of the second material layers that are exposed by the gate regions. 
     
     
         20 . The method as claimed in  claim 11 , wherein forming the conductive patterns comprises:
 forming a conductive layer filling the second opening and the gate regions; and   patterning the conductive layer to form the conductive patterns in the gate regions, respectively.