Methods of filling isolation trenches for semiconductor devices and resulting structures

Abstract

The invention relates to a method and resulting structure that can substantially minimize and/or eliminate void formation during an isolation trench isolation fill process for typical trench shaped and goal-post shaped isolation regions. First, a thin thermal oxidation layer is grown on the sidewall of each trench and then a layer of polysilicon is deposited above the oxidation layer and oxidized. In one embodiment, a repeating series of polysilicon deposition and polysilicon oxidation steps are performed until each trench has been completely filled. In another embodiment, within a goal-post shaped trench having a wider upper portion and a narrower lower portion, the remainder of the upper wider trench portion is filled using a conventional high density plasma technique.

1 - 13 . (canceled) 
     
     
         14 . A trench isolation region comprising:
 a trench;   an oxide layer on the sidewalls and bottom of the trench;   a first silicon oxide layer deposited above said oxide layer, said first silicon oxide layer being formed by oxidizing a polysilicon layer; and   an insulator layer formed above said first silicon oxide layer to fill the remainder of the trench.   
     
     
         15 . The trench isolation region of  claim 14 , wherein said insulator layer is a second silicon oxide layer formed by oxidizing another polysilicon layer. 
     
     
         16 . The trench isolation region of  claim 14 , wherein said insulator is formed by high density plasma deposition. 
     
     
         17 . The trench isolation region of  claim 15 , further comprising a third silicon oxide layer deposited above said second silicon oxide layer formed by oxidizing another polysilicon layer. 
     
     
         18 . The trench isolation region of  claim 16 , wherein before said insulator layer is formed, a second silicon oxide layer is deposited above said first silicon oxide layer, said second silicon oxide layer being formed by oxidizing a second polysilicon layer and then said insulator is formed by high density plasma deposition. 
     
     
         19 . The trench isolation region of  claim 14 , wherein said trench comprises a first upper trench portion and a second lower trench portion being below the upper trench portion, wherein the lower trench portion has a width less than the width of the upper trench portion. 
     
     
         20 . A memory device comprising:
 an active area; and   a trench isolation region adjacent said active area, said region comprising:   a trench;   an oxide layer on the sidewalls and bottom of the trench;   a first silicon oxide layer deposited above said oxide layer, said first silicon oxide layer being formed by oxidizing a polysilicon layer; and   an insulator layer formed above said first silicon oxide layer to fill the remainder of the trench.   
     
     
         21 . The memory device of  claim 20 , wherein said insulator layer is a second silicon oxide layer formed by oxidizing another polysilicon layer. 
     
     
         22 . The memory device of  claim 20 , wherein said insulator is formed by high density plasma deposition. 
     
     
         23 . The memory device of  claim 21 , further comprising a third silicon oxide layer deposited above said second silicon oxide layer formed by oxidizing another polysilicon layer. 
     
     
         24 . The memory device of  claim 20 , wherein said trench comprises a first upper trench portion and a second lower trench portion being below the upper trench portion, wherein the lower trench portion has a width less than the width of the upper trench portion. 
     
     
         25 . The memory device of  claim 20 , wherein the memory device is flash memory. 
     
     
         26 . The memory device of  claim 22 , wherein before said insulator layer is formed, a second silicon oxide layer is deposited above said first silicon oxide layer, said second silicon oxide layer being formed by oxidizing a second polysilicon layer and then said insulator is formed by high density plasma deposition. 
     
     
         27 . A system comprising:
 a processor; and   a memory device coupled to said processor, said memory device comprising:   an active area; and   a trench isolation region adjacent said active area, said region comprising:   a trench;   an oxide layer on the sidewalls and bottom of the trench;   a first silicon oxide layer deposited above said oxide layer, said first silicon oxide layer being formed by oxidizing a polysilicon layer; and   an insulator layer formed above said first silicon oxide layer to fill the remainder of the trench.   
     
     
         28 . The system of  claim 27 , wherein said insulator layer is a second silicon oxide layer formed by oxidizing another polysilicon layer. 
     
     
         29 . The system of  claim 27 , wherein said insulator is formed by high density plasma deposition. 
     
     
         30 . The system of  claim 28 , further comprising a third silicon oxide layer deposited above said second silicon oxide layer formed by oxidizing another polysilicon layer. 
     
     
         31 . The system of  claim 27 , wherein said trench comprises a first upper trench portion and a second lower trench portion being below the upper trench portion, wherein the lower trench portion has a width less than the width of the upper trench portion. 
     
     
         32 . The system of  claim 27 , wherein the memory device is flash memory. 
     
     
         33 . The system of  claim 29 , wherein before said insulator layer is formed, a second silicon oxide layer is deposited above said first silicon oxide layer, said second silicon oxide layer being formed by oxidizing a second polysilicon layer and then said insulator is formed by high density plasma deposition.