Architecture and implementation method of programmable arithmetic controller for cryptographic applications

Abstract

An architecture includes a controller. The controller is configured to receive a microprogram. The microprogram is configured for performing at least one of hierarchical or a sequence of polynomial computations. The architecture also includes an arithmetic logic unit (ALU) communicably coupled to the controller. The ALU is controlled by the controller. Additionally, the microprogram is compiled prior to execution by the controller, the microprogram is compiled into a plurality of binary tables, and the microprogram is programmed in a command language in which each command includes a first portion for indicating at least one of a command or data transferred to the ALU, and a second portion for including a control command to the controller. The architecture and implementation of the programmable controller may be for cryptographic applications, including those related to public key cryptography.

1 . An architecture comprising:
 a controller, the controller configured to receive a microprogram, the microprogram configured for performing at least one of hierarchical or a sequence of polynomial computations; and   an arithmetic logic unit (ALU) communicably coupled to the controller, the ALU controlled by the controller,   wherein the microprogram is compiled prior to execution by the controller, the microprogram is compiled into a plurality of binary tables, and the microprogram is programmed in a command language in which each command includes a first portion for indicating at least one of a command or data transferred to the ALU, and a second portion for including a control command to the controller.   
     
     
         2 . The architecture of  claim 1 , wherein the plurality of binary tables includes four binary tables. 
     
     
         3 . The architecture of  claim 1 , wherein the plurality of binary tables includes a PROGRAM ROM binary table, a LABEL ROM binary table, a FUNCTION ROM binary table, and an F_id DECODER binary table. 
     
     
         4 . The architecture of  claim 3 , wherein the PROGRAM ROM binary table includes binary code of the microprogram to be executed during runtime, the LABEL ROM binary table includes addresses of commands labeled in the microprogram, the FUNCTION ROM binary table includes addresses of functions and subfunctions as entry points to be called during execution, and the F_id DECODER includes indices of functions accessible for external control for decoding. 
     
     
         5 . The architecture of  claim 3 , wherein the microprogram includes indices for the LABEL ROM binary table and the FUNCTION ROM binary table, the indices requiring less memory than full addresses of commands. 
     
     
         6 . The architecture of  claim 1 , further including a hierarchical function library, the hierarchical function library storing separate blocks of subprograms and subfunctions in at least four levels of subprograms and subfunctions. 
     
     
         7 . The architecture of  claim 6 , wherein the at least four levels include a top level for including protocols, an application level for including relatively complex operational functionality, an arithmetic level for including operational functionality, and a ground level for including initial ALU operations. 
     
     
         8 . The architecture of  claim 7 , wherein only the ground level requires direct hardware support for implementation. 
     
     
         9 . A method comprising:
 programming a microprogram in a command language in which each microprogram command includes a first portion for indicating at least one of a command or data transferred to an arithmetic logic unit (ALU), and a second portion for including a control command to a controller;   compiling the microprogram into a plurality of binary tables, the microprogram configured for performing at least one of hierarchical or a sequence of polynomial computations;   executing the microprogram by a controller;   configuring at least one of the plurality of binary tables for including the code of the microprogram; and   configuring at least one of the plurality of binary tables for storing at least one address of a command labeled in the microprogram.   
     
     
         10 . The method of  claim 9 , further including configuring at least one of the plurality of binary tables for storing addresses of at least one of a function or a subfunction as an entry point for calling during execution of the microprogram. 
     
     
         11 . The method of  claim 9 , further including configuring at least one of the plurality of binary tables for decoding indices of functions accessible for external control. 
     
     
         12 . The method of  claim 9 , further including performing at least one of editing the microprogram or generating binary tables, during which a controller netlist remains unchanged. 
     
     
         13 . The method of  claim 9 , wherein compiling the microprogram into a plurality of binary tables includes compiling the microprogram into a PROGRAM ROM binary table, a LABEL ROM binary table, a FUNCTION ROM binary table, and an F_id DECODER binary table. 
     
     
         14 . The method of  claim 9 , wherein compiling the microprogram into a plurality of binary tables includes compiling the microprogram from a hierarchical function library. 
     
     
         15 . The method of  claim 14 , further including storing separate blocks of subprograms and subfunctions in at least four levels of subprograms and subfunctions, the at least four levels include a top level for including protocols, an application level for including relatively complex operational functionality, an arithmetic level for including operational functionality, and a ground level for including initial ALU operations. 
     
     
         16 . The method of  claim 15 , further comprising providing hardware support for only the ground level. 
     
     
         17 . A system comprising:
 a controller, the controller configured to receive a microprogram, the microprogram configured for performing at least one of hierarchical or a sequence of polynomial computations;   an arithmetic logic unit (ALU) communicably coupled to the controller, the ALU controlled by the controller; and   a command register communicably coupled to the controller, the command register controlled by the controller and configured for storing at least one of input data, output data, or internal registers,   wherein the microprogram is compiled prior to execution by the controller, the microprogram is compiled into four binary tables, and the microprogram is programmed in a command language in which each command includes a first portion for indicating at least one of a command or data transferred to the ALU, and a second portion for including a control command to the controller.   
     
     
         18 . The system of  claim 17 , wherein the four binary tables include a PROGRAM ROM binary table, a LABEL ROM binary table, a FUNCTION ROM binary table, and an F_id DECODER binary table. 
     
     
         19 . The system of  claim 18 , wherein the PROGRAM ROM binary table includes binary code of the microprogram to be executed during runtime, the LABEL ROM binary table includes addresses of commands labeled in the microprogram, the FUNCTION ROM binary table includes addresses of functions and subfunctions as entry points to be called during execution, and the F_id DECODER includes indices of functions accessible for external control for decoding. 
     
     
         20 . The system of  claim 18 , wherein the microprogram includes indices for the LABEL ROM binary table and the FUNCTION ROM binary table, the indices requiring less memory than full addresses of commands.