Support for Multiple Coherence Domains

Abstract

A number of coherence domains are maintained among the multitude of processing cores disposed in a microprocessor. A cache coherency manager defines the coherency relationships such that coherence traffic flows only among the processing cores that are defined as having a coherency relationship. The data defining the coherency relationships between the processing cores is optionally stored in a programmable register. For each source of a coherent request, the processing core targets of the request are identified in the programmable register. In response to a coherent request, an intervention message is forwarded only to the cores that are defined to be in the same coherence domain as the requesting core. If a cache hit occurs in response to a coherent read request and the coherence state of the cache line resulting in the hit satisfies a condition, the requested data is made available to the requesting core from that cache line.

1 . A microprocessor comprising:
 a plurality of processing cores; and   a cache coherency manager adapted to define a plurality of coherency relationships among the plurality of processing cores so that traffic characterized as being associated with a coherency relationship flows only between the processing cores defined as having the coherency relationship.   
     
     
         2 . The microprocessor of  claim 1  wherein in response to receiving a request from a first one of the plurality of processing cores, the cache coherency manager sends an intervention message to a first subset of the plurality of processing cores that is defined as having a coherency relationship with the first one of the plurality of processing cores, said first subset comprising the first one of the plurality of processing cores. 
     
     
         3 . The microprocessor of  claim 2  wherein said plurality of coherency relationships are defined in accordance with data supplied from a group consisting of programmable register, random access memory and hardwired circuitry. 
     
     
         4 . The microprocessor of  claim 2  wherein said cache coherency manager further comprises logic circuits adapted to:
 transfer a data identified by the request to the first one of the plurality of processing cores from a cache memory associated with a second one of the plurality of processing cores disposed in the first subset if the request is a read access request and the data is stored in the cache memory associated with the second one of the plurality of processing cores. 
 
     
     
         5 . The microprocessor of  claim 4  wherein said cache coherency manager further comprises logic circuits adapted to:
 transfer the data to the first one of the plurality of cores from one of a level-2 cache and a system memory if the data is not stored in the cache memories associated with the first subset. 
 
     
     
         6 . The microprocessor of  claim 3  wherein said cache coherency manager further comprises logic circuits adapted to maintain a first input/output device coherent with a second subset of the plurality of processing cores in accordance with the supplied data, said input/output device being coupled to the microprocessor via a system bus. 
     
     
         7 . The microprocessor of  claim 1  wherein at least one of the plurality of processing cores includes a single cache tag array. 
     
     
         8 . The microprocessor of  claim 2  wherein said cache coherency manager further comprises a logic block adapted to logically partition a main memory into a plurality of addressable regions each region being configured to store coherent data associated with a different one of the coherence relationships, said main memory being coupled to the microprocessor via a system bus. 
     
     
         9 . The microprocessor of  claim 2  wherein said cache coherency manager is configured to send the intervention message to the first subset of the plurality of processing cores in accordance with one of an identifier associated with the first one of the plurality of processing cores and an address defined by the request. 
     
     
         10 . A method of controlling coherent traffic among a plurality of processing cores disposed in a microprocessor, the method comprising:
 enabling flow of coherent traffic among first ones of the plurality of processing cores that are defined as having a coherency relationship; and   inhibiting flow of coherent traffic among second ones of the plurality of processing cores that are defined as not having a coherency relationship.   
     
     
         11 . The method of  claim 10  further comprising:
 receiving a first request from a first one of the plurality of processing cores; and 
 sending an intervention message to a first subset of the plurality of processing cores that is defined as having a coherency relationship with the first one of the plurality of cores; said first subset comprising the first one of the plurality of processing cores. 
 
     
     
         12 . The method of  claim 11  further comprising:
 transferring a data identified by the first request to the first one of the plurality of processing cores from a cache memory associated with a second one of the plurality of processing cores disposed in the first subset if the first request is a read request and the data is stored in the cache memory associated with the second one of the plurality of processing cores. 
 
     
     
         13 . The method of  claim 11  further comprising:
 maintaining coherency between a first input/output device and a second subset of the plurality of processing cores, said input/output device being coupled to the microprocessor via a system bus. 
 
     
     
         14 . The method of  claim 13  further comprising:
 maintaining cache coherency between the first one of the plurality of processing cores and the second one of the plurality of processing cores disposed in the microprocessor; 
 maintaining cache coherency between the first one of the plurality of processing cores and a third one of the plurality of processing cores disposed in the microprocessor; and 
 maintaining cache non-coherency between the second one of the plurality of processing cores and the third one of the plurality of processing cores. 
 
     
     
         15 . The method of  claim 11  further comprising:
 disposing a single cache tag array in at least one of the plurality of processing cores. 
 
     
     
         16 . The method of  claim 11  further comprising:
 defining the coherency relationship in accordance with data supplied from a group consisting of programmable register, random access memory and hardwired circuit. 
 
     
     
         17 . The method of  claim 11  further comprising:
 coupling a main memory to the microprocessor via a system bus; and 
 logically partitioning the main memory into a plurality of regions each adapted to store coherent data associated with a different one of a plurality of coherency relationships. 
 
     
     
         18 . The method of  claim 11  further comprising:
 sending the intervention message to the first subset of the plurality of processing cores in accordance with one of an identifier associated with the first one of the plurality of processing cores and an address defined by the request. 
 
     
     
         19 . A computer readable storage medium including instructions defining logic blocks of a microprocessor comprising a plurality of processing cores, the computer readable storage medium adapted for use by an electronic design automation application executed by a computer, wherein the logic blocks are configured to perform an operation comprising:
 enabling flow of coherent traffic among first ones of the plurality of processing cores that are defined as having a coherency relationship; and   inhibiting flow of coherent traffic among second ones of the plurality of processing cores that are defined as not having a coherency relationship.   
     
     
         20 . The computer readable storage medium of  claim 19  wherein the logic blocks are further adapted to perform an operation comprising:
 receiving a first request from a first one of the plurality of processing ores; and 
 sending an intervention message to a first subset of the plurality of processing cores that is defined as having a coherency relationship with the first one of the plurality of cores; said first subset comprising the first one of the plurality of processing cores. 
 
     
     
         21 . The computer readable storage medium of  claim 20  wherein the logic blocks are further adapted to perform an operation comprising:
 transferring a data identified by the first request to the first one of the plurality of processing cores from a cache memory associated with a second one of the plurality of processing cores disposed in the first subset if the first request is a read request and the data is stored in the cache memory associated with the second one of the plurality of processing cores. 
 
     
     
         22 . The computer readable storage medium of  claim 20  wherein the logic blocks are further adapted to perform an operation comprising:
 maintaining coherency between a first input/output device and a second subset of the plurality of processing cores, said input/output device being coupled to the microprocessor via a system bus. 
 
     
     
         23 . The computer readable storage medium of  claim 19  wherein at least one of the plurality of processing cores includes a single cache tag array. 
     
     
         24 . The computer readable storage medium of  claim 20  wherein the logic blocks are further adapted to perform an operation comprising:
 logically partitioning a main memory into a plurality of regions each adapted to store coherent data associated with a different one of a plurality of coherency relationships. 
 
     
     
         25 . The computer readable storage medium of  claim 20  wherein the logic blocks are further adapted to perform an operation comprising:
 sending the intervention message to the first subset of the plurality of processing cores in accordance with one of an identifier associated with the first one of the plurality of processing cores and an address defined by the request.