Inventor · disambiguated record
Ryan C. Kinter
Also filed as: KINTER RYAN C
29 granted patents·6 pending applications·445 citations·filing 2000–2018
97Inventor score
Top patents by PatentIndex Score
35 records- 0194US7853777B2Instruction/skid buffers in a multithreading microprocessor that store dispatched instructions to avoid re-fetching flushed instructionsMIPS TECH INC·Filed 2005·Granted Dec 14, 2010·43 cites·38 claims
- 0292US7752627B2Leaky-bucket thread scheduler in a multithreading microprocessorMIPS TECH INC·Filed 2005·Granted Jul 6, 2010·34 cites·39 claims
- 0390US7664936B2Prioritizing thread selection partly based on stall likelihood providing status information of instruction operand register usage at pipeline stagesMIPS TECH INC·Filed 2005·Granted Feb 16, 2010·26 cites·72 claims
- 0490US6430655B1Scratchpad RAM memory accessible in parallel to a primary cacheMIPS TECH INC·Filed 2000·Granted Aug 6, 2002·70 cites·35 claims
- 0589US7558939B2Three-tiered translation lookaside buffer hierarchy in a multithreading microprocessorMIPS TECH INC·Filed 2005·Granted Jul 7, 2009·21 cites·77 claims
- 0688US7660969B2Multithreading instruction scheduler employing thread group prioritiesMIPS TECH INC·Filed 2007·Granted Feb 9, 2010·17 cites·58 claims
- 0788US7657891B2Multithreading microprocessor with optimized thread scheduler for increasing pipeline utilization efficiencyMIPS TECH INC·Filed 2005·Granted Feb 2, 2010·18 cites·39 claims
- 0886US8131941B2Support for multiple coherence domainsKINTER RYAN C·Filed 2007·Granted Mar 6, 2012·15 cites·25 claims
- 0986US7627794B2Apparatus and method for discrete test access control of multiple coresMIPS TECH INC·Filed 2006·Granted Dec 1, 2009·14 cites·5 claims
- 1086US6836833B1Apparatus and method for discovering a scratch pad memory configurationMIPS TECH INC·Filed 2002·Granted Dec 28, 2004·43 cites·23 claims
- 1184US7613904B2Interfacing external thread prioritizing policy enforcing logic with customer modifiable register to processor internal schedulerMIPS TECH INC·Filed 2005·Granted Nov 3, 2009·14 cites·91 claims
- 1283US7925859B2Three-tiered translation lookaside buffer hierarchy in a multithreading microprocessorMIPS TECH INC·Filed 2009·Granted Apr 12, 2011·10 cites·25 claims
- 1382US7681014B2Multithreading instruction scheduler employing thread group prioritiesMIPS TECH INC·Filed 2005·Granted Mar 16, 2010·11 cites·53 claims
- 1481US7657708B2Methods for reducing data cache access power in a processor using way selection bitsMIPS TECH INC·Filed 2006·Granted Feb 2, 2010·11 cites·18 claims
- 1579US8151268B2Multithreading microprocessor with optimized thread scheduler for increasing pipeline utilization efficiencyJONES DARREN M·Filed 2010·Granted Apr 3, 2012·7 cites·16 claims
- 1677US8230202B2Apparatus and method for condensing trace information in a multi-processor systemBERG THOMAS BENJAMIN·Filed 2008·Granted Jul 24, 2012·12 cites·26 claims
- 1777US7769958B2Avoiding livelock using intervention messages in multiple core processorsMIPS TECH INC·Filed 2007·Granted Aug 3, 2010·8 cites·23 claims
- 1875US7650465B2Micro tag array having way selection bits for reducing data cache access powerMIPS TECH INC·Filed 2006·Granted Jan 19, 2010·7 cites·25 claims
- 1974US8392663B2Coherent instruction cache utilizing cache-op execution resourcesKINTER RYAN C·Filed 2008·Granted Mar 5, 2013·7 cites·20 claims
- 2074US7594089B2Smart memory based synchronization controller for a multi-threaded multiprocessor SoCMIPS TECH INC·Filed 2004·Granted Sep 22, 2009·20 cites·69 claims
- 2170US10782977B2Fault detecting and fault tolerant multi-threaded processorsMIPS TECH LLC·Filed 2018·Granted Sep 22, 2020·1 cites·25 claims
- 2269US7315937B2Microprocessor instructions for efficient bit stream extractionsMIPS TECH INC·Filed 2004·Granted Jan 1, 2008·17 cites·39 claims
- 2367US7707389B2Multi-ISA instruction fetch unit for a processor, and applications thereofMIPS TECH INC·Filed 2003·Granted Apr 27, 2010·12 cites·44 claims
- 2454US7873810B2Microprocessor instruction using address index values to enable access of a virtual buffer in circular fashionMIPS TECH INC·Filed 2004·Granted Jan 18, 2011·3 cites·25 claims
- 2553US6961819B2Method and apparatus for redirection of operations between interfacesMIPS TECH INC·Filed 2002·Granted Nov 1, 2005·4 cites·45 claims
- 2651US2009249046A1Apparatus and method for low overhead correlation of multi-processor trace informationMIPS TECH INC·Filed 2008·Application pending·0 cites
- 2750US2013031314A1Support for Multiple Coherence DomainsMIPS TECH INC·Filed 2012·Application pending·0 cites
- 2848US7509456B2Apparatus and method for discovering a scratch pad memory configurationMIPS TECH INC·Filed 2004·Granted Mar 24, 2009·0 cites·16 claims
- 2947US7739455B2Avoiding livelock using a cache manager in multiple core processorsMIPS TECH INC·Filed 2007·Granted Jun 15, 2010·0 cites·21 claims
- 3046US2008320233A1Reduced Handling of Writeback DataMIPS TECH INC·Filed 2007·Application pending·0 cites
- 3145US7634619B2Method and apparatus for redirection of operations between interfacesMIPS TECH INC·Filed 2005·Granted Dec 15, 2009·0 cites·25 claims
- 3245US2005182903A1Apparatus and method for preventing duplicate matching entries in a translation lookaside bufferMIPS TECH INC·Filed 2004·Application pending·0 cites
- 3345US2013067284A1Apparatus and Method for Low Overhead Correlation of Multi-Processor Trace InformationBERG THOMAS BENJAMIN·Filed 2012·Application pending·0 cites
- 3442US7711926B2Mapping system and method for instruction set processingMIPS TECH INC·Filed 2001·Granted May 4, 2010·0 cites·23 claims
- 3540US2012290780A1Multithreaded Operation of A Microprocessor CacheKINTER RYAN C·Filed 2012·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →