System and method for providing more logical memory ports than physical memory ports

Abstract

Some embodiments provide for a method of mapping a user design to a configurable integrated circuit (IC). The method is for a configurable IC that implements a user design with an associated user design clock cycle. The IC operates on a sub-cycle clock that has multiple sub-cycle periods within a user period of the user design clock cycle. The method identifies multiple port accesses to a first multi-port memory defined in the user design. The accesses are in a single user design clock cycle. The method maps the multiple port accesses to the first multi-port memory to multiple physical-port memory accesses to a second physical-port memory in the configurable IC during multiple sub-cycles associated with a single user design clock cycle.

1 - 20 . (canceled) 
     
     
         21 . A configurable integrated circuit (IC) comprising:
 an array of configurable tiles comprising columns and rows of configurable tiles;   a plurality of sets of non-neighboring offset connections (NNOCs), each NNOC connecting two tiles that are not vertically or horizontally aligned, each set of NNOCs converging on input loci of one configurable tile.   
     
     
         22 . The configurable IC of  claim 21 , wherein a first set of NNOCs is sourced by a first set of sourcing configurable tiles and received by a first receiving configurable tile, wherein a second set of NNOCs is sourced by a second set of sourcing configurable tiles and received by a second receiving configurable tile, wherein the relative positions of the first set of sourcing configurable tiles with respect to the first receiving configurable tile are identical to the relative positions of the second set of sourcing configurable tiles with respect to the second receiving configurable tile. 
     
     
         23 . The configurable IC of  claim 21 , wherein each set of NNOCs are sourced by multiple output loci of another configurable tile. 
     
     
         24 . The configurable IC of  claim 23 , wherein at least one output locus is an output of a routing multiplexer (RMUX) in the other configurable tile. 
     
     
         25 . The configurable IC of  claim 23 , wherein at least one output locus is an output of a look-up table (LUT) in the other configurable tile. 
     
     
         26 . The configurable IC of  claim 21 , wherein the array of configurable tiles and the plurality of sets of NNOCs are configured as a barrel-shifter. 
     
     
         27 . The configurable IC of  claim 21 , wherein each set of NNOCs is sourced by a plurality of other configurable tiles. 
     
     
         28 . A configurable integrated circuit (IC) comprising:
 an array of configurable tiles comprising columns and rows of configurable tiles;   a plurality of sets of non-neighboring offset connections (NNOCs), each NNOC connecting two tiles that are not vertically or horizontally aligned, wherein each set of NNOCs is sourced by an output locus of a configurable tile.   
     
     
         29 . The configurable IC of  claim 28 , wherein a first set of NNOCs is sourced by a first sourcing configurable tile and received by a first set of receiving configurable tiles, wherein a second set of NNOCs is sourced by a second sourcing configurable tile and received by a second set of receiving configurable tiles, wherein the relative positions of the first set of receiving configurable tiles with respect to the first sourcing configurable tile are identical to the relative positions of the second set of receiving configurable tiles with respect to the second sourcing configurable tile. 
     
     
         30 . The configurable IC of  claim 28 , wherein each set of NNOCs sourced by an output locus of a configurable tile is received by multiple input loci of another configurable tile. 
     
     
         31 . The configurable IC of  claim 30 , wherein each input locus of the other configurable tile is an input of a multiplexer in the other configurable tile. 
     
     
         32 . The configurable IC of  claim 30 , wherein the input loci of the other configurable tile are inputs of input multiplexers (IMUXs) and routing multiplexers (RMUXs). 
     
     
         33 . The configurable IC of  claim 28 , wherein the array of configurable tiles and the plurality of sets of NNOCs are configured as a barrel-shifter. 
     
     
         34 . The configurable IC of  claim 28 , wherein each set of NNOCs is received by a plurality of other configurable tiles. 
     
     
         35 . A configurable integrated circuit (IC) comprising:
 an array of configurable tiles comprising columns and rows of configurable tiles;   a plurality of non-neighboring offset connections (NNOCs), each NNOC of said plurality NNOCs connecting two tiles of said plurality of configurable tiles, said two connected tiles are offset from each other by at least two rows and at least one column, each tile of a plurality of configurable tiles in the array receiving a first plurality of NNOCs and sourcing a second plurality of NNOCs.   
     
     
         36 . The configurable IC of  claim 35 , wherein the configurable tile sources the second plurality of NNOCs from at least an output of a look-up table (LUT) in the configurable tile. 
     
     
         37 . The configurable IC of  claim 35 , wherein the configurable tile sources the second plurality of NNOCs from at least an output of a multiplexer in the configurable tile. 
     
     
         38 . The configurable IC of  claim 35 , wherein the configurable tile receives the first plurality of NNOCs at a plurality of multiplexers. 
     
     
         39 . The configurable IC of  claim 38 , wherein at least one of the plurality of multiplexer is an input multiplexer (IMUX) of the configurable tile. 
     
     
         40 . The configurable IC of  claim 38 , wherein at least one of the plurality of multiplexer is a routing multiplexer (RMUX) of the configurable tile. 
     
     
         41 . The configurable IC of  claim 35 , wherein the plurality of configurable tiles are configured as a barrel-shifter. 
     
     
         42 . The configurable IC of  claim 41 , wherein the barrel shifter is for accessing a wide and shallow physical memory in the IC as a narrow and deep logical memory, wherein the logical memory has more words than the physical memory.