Integrated circuit system including nitride layer technology

Abstract

An integrated circuit method for manufacturing an integrated circuit system including loading a wafer into a processing chamber and pre-purging the processing chamber with a first ammonia gas. Depositing a first nitride layer over the wafer and purging the processing chamber with a second ammonia gas. Depositing a second nitride layer over the first nitride layer that is misaligned with the first nitride layer. Post-purging the processing chamber with a third ammonia gas and purging the processing chamber with a nitrogen gas.

1 . An integrated circuit system comprising:
 providing a substrate including a core region, an I/O region and a SONOS region;   forming a bottom silicon oxide layer over the substrate;   forming a bottom silicon nitride layer over the bottom silicon oxide layer;   forming a top silicon oxide layer by high temperature oxidation over the bottom silicon nitride layer;   forming a top silicon nitride layer over the top silicon oxide layer;   forming a first etch mask over the SONOS region;   etching the top silicon nitride layer, the top silicon oxide layer and the bottom silicon nitride layer formed over the core region and the I/O region without substantial damage to the bottom silicon oxide layer due to the misalignment of the first nitride layer and the second nitride layer;   removing the first etch mask from over the SONOS region and forming a second etch mask over the core region and the I/O region;   etching the top silicon nitride layer formed over the SONOS region;   removing the second etch mask and the bottom silicon oxide layer formed over the core region and the I/O region; and   forming gate structures over the core region, the I/O region and the SONOS region.   
     
     
         2 . The system as claimed in  claim 1  wherein:
 forming the top silicon oxide layer by high temperature oxidation passivates the bottom silicon nitride layer. 
 
     
     
         3 . The system as claimed in  claim 1  wherein:
 forming the top silicon oxide layer by high temperature oxidation prevents etching of the bottom silicon oxide layer during etching of the top silicon oxide layer. 
 
     
     
         4 . The system as claimed in  claim 1  wherein:
 forming the top silicon oxide layer by high temperature oxidation prevents silicon pitting of the substrate during subsequent etching steps. 
 
     
     
         5 . The system as claimed in  claim 1  wherein:
 forming the top silicon oxide layer by high temperature oxidation prevents failure of gate oxides. 
 
     
     
         6 . An integrated circuit system comprising:
 providing a substrate including a core region, an I/O region and a SONOS region;   forming a bottom silicon oxide layer over the substrate;   forming a silicon nitride layer over the bottom silicon oxide layer;   forming a top silicon oxide layer over the silicon nitride layer;   forming an etch mask over the SONOS region;   etching the top silicon oxide layer formed over the core region and the I/O region without substantial damage to the bottom silicon oxide layer due to the misalignment of the first nitride layer and the second nitride layer;   removing the etch mask from over the SONOS region;   etching the silicon nitride layer formed over the core region and the I/O region by a hot phosphoric acid treatment;   removing the bottom silicon oxide layer formed over the core region and the I/O region; and   forming gate structures over the core region, the I/O region and the SONOS region.   
     
     
         7 . The system as claimed in  claim 6  wherein:
 etching the silicon nitride layer formed over the the core region and the I/O region by a hot phosphoric acid treatment prevents pitting of the substrate. 
 
     
     
         8 . The system as claimed in  claim 6  wherein:
 etching the silicon nitride layer formed over the the core region and the I/O region by a hot phosphoric acid treatment prevents failure of gate oxides. 
 
     
     
         9 . The system as claimed in  claim 6  wherein:
 etching the silicon nitride layer includes a hot phosphoric acid treatment employing about 55 to about 85 percent phosphoric acid by volume. 
 
     
     
         10 . The system as claimed in  claim 6  wherein:
 forming the silicon nitride layer includes multiple separate deposition steps, which causes microscopic discontinuities formed within each layer to misalign.