Semiconductor Device and Manufacturing Method thereof

Abstract

The present invention provides a semiconductor device, comprising: a substrate; shallow trench isolations embedded into the substrate and forming at least one opening area; a channel region located in the opening area; a gate stack comprising a gate dielectric layer and a gate electrode layer and located above the channel region; source/drain regions located at both sides of the channel region and comprising a stress layer that provides a strain to the channel region; wherein, there is a liner layer between the shallow trench isolation and the stress layer, which serves as the seed layer of the stress layer. A liner layer that is of the same or similar material as the stress layer in the source/drain region is inserted between the STI and the stress layer of the source/drain region as a seed layer or nucleation layer for the epitaxial growth, thereby eliminating the STI edge effect during the source/drain strain engineering, i.e. eliminating the gap between the STI and the stress layer of the source/drain region, as a result, the reduction of the channel stress produced by the source/drain strain is prevented, the carrier mobility of the MOS device is increased and the driving capability of the device is enhanced.

1 . A semiconductor device, comprising:
 a substrate;   shallow trench isolations embedded into the substrate and forming at least one opening area;   a channel region located in the opening area;   a gate stack comprising a gate dielectric layer and a gate electrode layer, the gate stack being located above the channel region;   source/drain regions located at both sides of the channel region and comprising a stress layer that provides a strain to the channel region;   wherein, there is a liner layer between the shallow trench isolation and the stress layer, which serves as the seed layer of the stress layer.   
     
     
         2 . The semiconductor device according to  claim 1 , wherein with respect to the pMOSFET, the stress layer comprises an epitaxially grown Si 1-x Ge x , and with respect to the nMOSFET, the stress layer comprises an epitaxially grown Si 1-y C y , wherein x and y are both greater than 0 but smaller than 1. 
     
     
         3 . The semiconductor device according to  claim 1 , wherein the liner layer comprises Si 1-x Ge x , Si 1-x-y Ge x C y  or Si 1-y C y , wherein x and y are both greater than 0 but smaller than 1. 
     
     
         4 . The semiconductor device according to  claim 3 , wherein x is in the range of 0.15 to 0.7, and y is in the range of 0.002 to 0.02. 
     
     
         5 . The semiconductor device according to  claim 1 , wherein the liner layer has a thickness of 1-20 nm. 
     
     
         6 . The semiconductor device according to  claim 1 , wherein the stress region is flush with the top of the shallow trench isolation. 
     
     
         7 . A method for manufacturing the semiconductor device of  claim 1 , comprising:
 forming shallow trenches in the substrate;   epitaxially growing a liner layer selectively in the shallow trench so as to be used as the seed layer of a stress layer;   forming an isolation material on the liner layer in the shallow trench to form shallow trench isolations, said shallow trench isolations surrounding at least one opening area;   forming a gate stack in the opening area;   forming source/drain regions at both sides of the gate stack, wherein a place between the source/drain regions under the gate stack serves as a channel region, and said source/drain regions comprise a stress layer for providing a strain to the channel region.   
     
     
         8 . The method of  claim 7 , wherein, with respect to the pMOSFET, the stress layer comprises an epitaxially grown Si 1-x Ge x , with respect to the nMOSFET, the stress layer comprises an epitaxially grown Si 1-y C y , wherein both x and y are greater than 0 but smaller than 1. 
     
     
         9 . The method of  claim 7 , wherein said liner layer comprises Si 1-x Ge x , Si 1-x-y Ge x C y  or Si 1-y C y , wherein both x and y are greater than 0 but smaller than 1. 
     
     
         10 . The method of  claim 9 , wherein x is in the range of 0.15 to 0.7, y is in the range of 0.002 to 0.02. 
     
     
         11 . The method of  claim 7 , wherein the liner layer has a thickness of 1-20 nm. 
     
     
         12 . The method of  claim 7 , wherein the stress layer is flush with the top of the shallow trench isolation. 
     
     
         13 . The method of  claim 7 , wherein the isolation material is silicon dioxide. 
     
     
         14 . The method of  claim 7 , wherein the steps of forming the source/drain regions include: etching the substrate to form trenches for the source/drain regions, and epitaxially growing the stress layer in the trenches for the source/drain regions.