System with a defect tolerant configurable ic

Abstract

Some embodiments of the invention provide a system that includes a first defect tolerant configurable integrated circuit and a second IC communicatively coupled to the defect tolerant configurable first IC.

1 . A system comprising:
 a) a first defect tolerant configurable integrated circuit; and   b) a second IC communicatively coupled to the defect tolerant configurable first IC.   
     
     
         2 . The system of  claim 1 , wherein the defect tolerant configurable IC comprises a set of defective components. 
     
     
         3 . The system of  claim 2 , wherein at least one defective component from the set of defective components is a logic circuit. 
     
     
         4 . The system of  claim 2 , wherein at least one defective component from the set of defective components is an interconnect circuit. 
     
     
         5 . The system of  claim 1 , wherein the system is a programmable system in a package (“PSiP”) that includes the first and second IC's in one package. 
     
     
         6 . The system of  claim 5 , wherein the PSiP includes a substrate on top of which the first and second IC's are mounted. 
     
     
         7 . The system of  claim 6 , wherein the PSiP includes a covering for covering the top of the substrate and the first and second IC's. 
     
     
         8 . The system of  claim 7 , wherein the covering is a cap that encapsulates the top of the substrate and the IC's to form a housing that contains the first and second ICs. 
     
     
         9 . The system of  claim 7 , wherein the covering is a covering fill that covers the top of the substrate and the first and second ICs. 
     
     
         10 . The system of  claim 9 , wherein the covering fill completely covers the first and second ICs. 
     
     
         11 . The system of  claim 9 , wherein the covering fill leaves a portion of at least one IC exposed. 
     
     
         12 . The system of  claim 1 , wherein the defect tolerant configurable IC is a reconfigurable IC. 
     
     
         13 . The system of  claim 12 , wherein the reconfigurable IC operates at a first clock rate that is faster than a second clock rate of another one of the IC's. 
     
     
         14 . The system of  claim 12 , wherein the reconfigurable IC implements an IC that is designed for a first clock rate, wherein the reconfigurable IC operates at a second clock rate that is faster than the second clock rate. 
     
     
         15 . The system of  claim 14 , wherein the first clock rate is the rate of a first clock, wherein the reconfigurable IC reconfigures multiple times within a clock cycle of the first clock.