Series and parallel hybrid switched capacitor networks for ic power delivery

Abstract

Series switches for power delivery. A regulator operated as a current source is arranged in parallel with a switched capacitor divider. A switched capacitor divider is configured in series with a plurality of linear regulators with each regulating one of a plurality of voltage outputs from the switched capacitor divider. In another embodiment, a series switch bridge has a first pair of switches connected in series with a second pair of switches across a voltage input, each switch within a pair of switches is switched in-phase with the other while the first pair of switches is switched out of phase with the second pair of switches. A balancing capacitor is coupled across one switch in both the first and second pair to be in parallel when either of the pair of switches is closed to reduce a charge imbalance between the switches.

1 . A power delivery network to deliver power to one or more integrated circuits at a plurality of voltages, the network comprising:
 a switched capacitor divider (SCD) comprising:
 a plurality of FETs configured with drain terminals coupled with source terminals to be in series across a voltage input; and 
 a plurality of capacitors connected across the voltage input and coupled with the plurality of FETs to divide the voltage input into a plurality of first voltage outputs; and 
   a plurality of linear regulators, each of the plurality of linear regulators coupled with one of the plurality of first voltage outputs to regulate a second voltage output.   
     
     
         2 . The power delivery network of  claim 1 , wherein alternating ones of the plurality of FETs have gate terminals coupled together to form a first and second pair of gate coupled FETs, and wherein the first pair of gate coupled FETs is configured to switch between a low state and a high state within a switching cycle while the second pair of gate coupled FETs is configured to switch to a state opposite the first pair of gate coupled FETs; and wherein the plurality of capacitors further comprise:
 a first capacitor coupled to a drain terminal of each of the first pair of gate coupled FETs; and   a second capacitor coupled to a drain terminal of each of the second pair of gate coupled FETs, both of the first and second capacitors to be alternately charged and discharged within the switching cycle when the first and second pairs of gate coupled FETs are switched between low and high states.   
     
     
         3 . The power delivery network of  claim 1 , further comprising a buck regulator stage to provide the voltage input to the SCD. 
     
     
         4 . The power delivery network of  claim 1 , further comprising a linear regulator stage to provide the voltage input to the SCD. 
     
     
         5 . The power delivery network of  claim 1 , wherein each of the plurality of linear regulators is coupled to an output circuit including one of the one or more integrated circuits. 
     
     
         6 . The power delivery network of  claim 1 , wherein the SCD is a divide-by-4 switched capacitor divider. 
     
     
         7 . The power delivery network of  claim 1 , wherein the plurality of FETs comprise a plurality of low voltage logic MOSFETs. 
     
     
         8 . The power delivery network of  claim 1 , wherein at least one of the one or more integrated circuits is a microprocessor. 
     
     
         9 . A power delivery network to power an integrated circuit, comprising:
 a voltage input; and   a series switch bridge, wherein the series switch bridge further comprises: a first pair of switches connected in series with a second pair of switches across the voltage input, wherein each of the first and second pairs of switches includes a first switch having a drain terminal coupled with a source terminal of a second switch with gate terminals coupled together, and wherein the first pair of switches is configured to switch between a low state and a high state within a switching cycle while the second pair of switches is configured to switch to a state opposite the first pair;   a balancing capacitor coupled with a node between the switches of the first pair and coupled with a node between the switches of the second pair; and   a voltage output coupled with a node between the first pair of switches and the second pair of switches, the voltage output to be coupled with the integrated circuit to be powered.   
     
     
         10 . The power delivery network of  claim 9 , wherein the voltage input is at least 3V and the switches are low voltage logic FETs configured to operate at approximately 1.5V. 
     
     
         11 . The power delivery network of  claim 9 , wherein the balancing capacitor has a capacitance value at least an order of magnitude larger than a parasitic output capacitance of any switch of the first and second switch pairs. 
     
     
         12 . The power delivery network of  claim 9 , wherein the balancing capacitor has a capacitance value at least two orders of magnitude larger than a parasitic output capacitance of any switch of the first and second switch pairs. 
     
     
         13 . The power delivery network of  claim 9 , wherein the series switch bridge is integrated with low voltage CMOS FETs onto a package of the integrated circuit. 
     
     
         14 . The power delivery network of  claim 9 , wherein the first pair and second pair of switches comprises a bridge circuit providing an output voltage equal to approximately half the voltage input. 
     
     
         15 . The power delivery network of  claim 9 , wherein the series switch bridge is a component of a voltage regulator.