Memory/logic conjugate system

Abstract

In a memory/logic conjugate system, a plurality of cluster memory chips each including a plurality of cluster memories ( 20 ) including basic cells ( 10 ) arranged in a cluster, the basic cell including a memory circuit, and a controller chip that controls the plurality of cluster memories are three-dimensionally stacked, the plurality of cluster memories located along the stacking direction of the plurality of cluster memory chips and the controller chip are electrically coupled to the controller chip via a multibus ( 11 ) including a through-via, an arbitrary one of the basic cells is directly accessed through the multibus from the controller chip so that truth value data is written therein, and whereby the arbitrary basic cell is switched to a logic circuit as conjugate.

1 . A memory/logic conjugate system comprising:
 a memory circuit including a plurality of memory bits;   an internal bus coupled to the memory circuit;   a basic cell including the memory circuit and the internal bus;   a plurality of cluster memories each including a plurality of the basic cells arranged in a cluster;   a multibus coupling the plurality of cluster memories; and   a controller that controls the plurality of cluster memories, wherein   the controller accesses an arbitrary one of the basic cells through the multibus and writes truth value data into the memory circuit via the internal bus, thereby the controller switches the arbitrary basic cell to a logic circuit as conjugate.   
     
     
         2 . The memory/logic conjugate system according to  claim 1 , wherein the basic cell includes a path setting register and a switch, the path setting register and the switch controls a connection of the internal bus. 
     
     
         3 . The memory/logic conjugate system according to  claim 1 , wherein the basic cell includes:
 the memory circuit;   the internal bus coupled to the memory circuit; and   further includes a path setting unit that controls a connection of the internal bus.   
     
     
         4 . The memory/logic conjugate system according to  claim 1 , wherein the plurality of cluster memories, the multibus and the controller are arranged on one chip. 
     
     
         5 . The memory/logic conjugate system according to  claim 1 , wherein the path setting unit includes a switch, a path setting register that controls the switch, and a mode selector. 
     
     
         6 . The memory/logic conjugate system according to  claim 1 , wherein the memory circuit is configured to at least a Volatile Memory. 
     
     
         7 . The memory/logic conjugate system according to  claim 1 , wherein the memory circuit is configured to at least a Non Volatile Memory. 
     
     
         8 . The memory/logic conjugate system according to  claim 1 , wherein
 the controller that includes a plurality of control circuits,   the multibus that includes a plurality of multibus wires, and   each of the plurality of control circuits controls the plurality of cluster memories coupled via the plurality of multibus wires corresponding thereto, respectively.   
     
     
         9 . The memory/logic conjugate system according to  claim 3 , further comprising a first control signal, wherein
 the first control signal is supplied to the memory circuit through the multibus and the internal bus,   the basic cell is switched to a forced memory mode (A) when the first control signal is at a predetermined first level, and   the basic cell is switched to a system mode (B) when the first control signal is at a predetermined second level that is different from the first level.   
     
     
         10 . The memory/logic conjugate system according to  claim 9 , wherein
 in the forced memory mode (A), the memory circuit becomes directly controllable from the multibus by inputting an address signal, a data input signal, and a control signal from the multibus to an input terminal of the memory circuit.   
     
     
         11 . The memory/logic conjugate system according to  claim 10 , wherein
 in the system mode (B), the address signal, the data input signal, and the control signal in the forced memory mode (A) are blocked, and a signal that inputs to the logic circuit is controlled by the path setting unit,   the system mode (B) includes a memory mode (B- 1 ) and a logic mode (B- 2 ),   the memory mode (B- 1 ) includes an external memory mode (B- 1 - 1 ) and a path setting register write mode (B- 1 - 2 ), and   the logic mode (B- 2 ) includes at least one of a computation mode (B- 2 - 1 ), a combined circuit mode (B- 2 - 2 ), an internal memory mode (B- 2 - 3 ) which is a memory invisible from outside, a logic Lib mode (B- 2 - 4 ), and a path setting register information change mode (B- 2 - 5 ).   
     
     
         12 . A memory/logic conjugate system comprising:
 a first cluster memory including a first basic cells arranged in a cluster, each of the first basic cells including a first memory circuit and a first internal bus connected to the first memory circuit;   a first bus interface electrically coupled to the first cluster memory;   a first cluster memory region that arranges the first cluster memory and the first bus interface formed therein;   a first wire arranged in the first cluster memory region and electrically coupled to the first bus interface;   a second cluster memory including a second basic cells arranged in a cluster, each of the second basic cells including a second memory circuit and a second internal bus coupled to the second memory circuit;   a second bus interface electrically coupled to the second cluster memory;   a second cluster memory region that arranges the second cluster memory and the second bus interface formed therein; and   a second wire arranged in the second cluster memory region and electrically coupled to the second bus interface, wherein   the first wire is electrically coupled to the second wire.   
     
     
         13 . The memory/logic conjugate system according to  claim 12 , wherein
 an arbitrary one of the first and second basic cells is accessed through corresponding the first and second wires and corresponding the first and second bus interfaces so that truth value data is written therein via corresponding the first or second internal buses, and whereby the arbitrary basic cell is switched to a logic circuit as conjugate.   
     
     
         14 . The memory/logic conjugate system according to  claim 12 , wherein the first and second basic cells includes a first and a second path setting registers and a first and a second switches, which controls a connection of the first and second internal buses corresponding thereto, respectively. 
     
     
         15 . The memory/logic conjugate system according to  claim 12 , wherein the first and second basic cells includes:
 the first and second memory circuits corresponding thereto, respectively;   the first and second internal buses connected to the first and second memory circuits, respectively; and   further includes a first and a second path setting unit that controls a connection of the first and second internal buses, respectively.   
     
     
         16 . The memory/logic conjugate system according to  claim 15 , wherein the first and second path setting units includes a first and a second switches, a first and a second path setting registers that controls the first and second switches, and a first and a second mode selectors, respectively. 
     
     
         17 . The memory/logic conjugate system according to  claim 12 , wherein the first and second cluster memories, the first and second bus interfaces and the first and second wires are arranged on one chip. 
     
     
         18 . The memory/logic conjugate system according to  claim 12 , wherein at least one of the first and second memory circuits is configured to at least a Volatile Memory. 
     
     
         19 . The memory/logic conjugate system according to  claim 12 , wherein at least one of the first and second memory circuits is configured to at least a Non Volatile Memory. 
     
     
         20 . A memory/logic conjugate system comprising:
 a first cluster memory including first basic cells arranged in a cluster, each of the first basic cells including a first memory circuit;   a first bus interface electrically coupled to the first cluster memory;   a second cluster memory including second basic cells arranged in a cluster, each of the second basic cells including a second memory circuit;   a second bus interface electrically coupled to the second cluster memory;   a first control circuit that controls the first and second cluster memories;   a first local bus electrically interconnecting the first control circuit and the first and second bus interfaces;   a third cluster memory including third basic cells arranged in a cluster, each of the third basic cells including a third memory circuit;   a third bus interface electrically coupled to the third cluster memory;   a fourth cluster memory including fourth basic cells arranged in a cluster, each of the fourth basic cells including a fourth memory circuit;   a fourth bus interface electrically coupled to the fourth cluster memory;   a second control circuit that controls the third and fourth cluster memories;   a second local bus electrically interconnecting the second control circuit and the third and fourth bus interfaces;   a global bus electrically coupling the first control circuit and the second control circuit; and   a central control circuit electrically coupled to the global bus to control and manage the first to fourth cluster memories.   
     
     
         21 . The memory/logic conjugate system according to  claim 20 , wherein
 an arbitrary one of the first to fourth basic cells is directly accessed through the first local bus or the second local bus so that truth value data is written therein, and whereby the arbitrary basic cell is switched to a logic circuit as conjugate.   
     
     
         22 . The memory/logic conjugate system according to  claim 20 , wherein the first to the fourth cluster memories, the first to the fourth bus interfaces, the first and second local buses, the first and second control circuits, the global bus and the central control circuit are arranged on one chip. 
     
     
         23 . The memory/logic conjugate system according to  claim 20 , wherein at least one of the first to the fourth memory circuits is configured to at least a Volatile Memory. 
     
     
         24 . The memory/logic conjugate system according to  claim 20 , wherein at least one of the first to the fourth memory circuits is configured to at least a Non Volatile Memory. 
     
     
         25 . The memory/logic conjugate system according to  claim 20 , wherein the first and third cluster memories and the first and third bus interfaces are formed on a first cluster memory chip,
 the second and fourth cluster memories and the second and fourth bus interfaces are formed on the second cluster memory chip,   the first local bus includes at least one of a first through-via formed on the first cluster memory chip and a second through-via formed on the second cluster memory chip,   the second local bus includes at least one of a third through-via formed on the first cluster memory chip and a fourth through-via formed on the second cluster memory chip, and   each of the first to fourth through-vias that penetrates corresponding to the first and second cluster memory chips.   
     
     
         26 . The memory/logic conjugate system according to  claim 25 , wherein the central control circuit, the first and second control circuits, and the global bus are formed on a controller chip, and
 the controller chip, the first and second cluster memory chips are formed by stacking.   
     
     
         27 . The memory/logic conjugate system according to  claim 20 , wherein the first to fourth cluster memories and the first to fourth bus interfaces are formed on a cluster memory chip, and
 the central control circuit, the first and second control circuits, and the global bus are formed on a controller chip, and   the controller chip and the cluster memory chip are formed by stacking.