Fabrication method for carrier substrate, printed circuit board using the same, and fabrication method thereof

Abstract

A method for fabricating a carrier substrate, a method for fabricating a printed circuit board using the carrier substrate and related printed circuit board. The method for fabricating the carrier substrate includes: providing an insulating base material with a copper foil layer formed on at least one surface thereof; stacking a metal layer having a length shorter than that of the copper foil layer on the copper foil layer; and forming an insulating layer on the metal layer.

1 . A method for fabricating a carrier substrate, the method comprising:
 providing an insulating base material with a copper foil layer formed on at least one surface thereof;   stacking a metal layer having a length shorter than that of the copper foil layer on the copper foil layer; and   forming an insulating layer on the metal layer.   
     
     
         2 . The method of  claim 1 , wherein the metal layer is made of at least one selected from the group consisting of gold (Au), silver (Ag), zinc (Zn), palladium (Pd), ruthenium (Ru), nickel (Ni), rhodium (Rh), a lead (Pb) /tin (Sn) alloy, and a nickel (Ni)/gold (Au) alloy. 
     
     
         3 . The method of  claim 1 , further comprising stacking a second copper foil layer on the insulating layer after the formation of the insulating layer. 
     
     
         4 . The method of  claim 1 , further comprising compressing the insulating layer after the formation of the insulating layer. 
     
     
         5 . A method for fabricating a printed circuit board, the method comprising:
 providing a carrier substrate including an insulating base material with a copper foil layer formed on at least one surface thereof, a metal layer formed on the cooper layer and having a length shorter than that of the copper foil layer, and an insulating layer formed on the metal layer;   forming a first circuit layer including a via having an upper land provided on the insulating layer and a first circuit pattern providing on a first face of the insulating layer;   separating the carrier substrate and the insulating layer; and   forming a second circuit layer including a second circuit pattern formed on a second face of the insulating layer, having a line width smaller than a minimum diameter of the via, and connected with the via.   
     
     
         6 . The method of  claim 5 , wherein the separating of the carrier substrate and the insulating layer is performed by cutting an inner side of an end portion of the metal layer. 
     
     
         7 . The method of  claim 5 , wherein the via is formed such that its diameter becomes smaller toward the second circuit pattern from the upper land. 
     
     
         8 . The method of  claim 5 , wherein the metal layer is made of at least one selected from the group consisting of gold (Au), silver (Ag), zinc (Zn), palladium (Pd), ruthenium (Ru), nickel (Ni), rhodium (Rh), a lead (Pb) /tin (Sn) alloy, and a nickel (Ni)/gold (Au) alloy. 
     
     
         9 . The method of  claim 5 , further comprising stacking a second copper foil layer on the insulating layer after the formation of the insulating layer. 
     
     
         10 . The method of  claim 5 , further comprising compressing the insulating layer after the formation of the insulating layer. 
     
     
         11 . The method of  claim 5 , wherein the forming of the first circuit layer comprises:
 forming a via hole at the insulating layer;   forming a first plated seed layer on the insulating layer and the via hole;   forming a first dry film pattern for the formation of the upper land and a second dry film pattern for the formation of the first circuit pattern on the first plated seed layer; and   performing electroplating to form the first circuit layer.   
     
     
         12 . The method of  claim 11 , wherein the forming of the first and second dry film patterns comprises:
 forming a dry film resist on the first plated seed layer; and exposing and developing the first film resist.   
     
     
         13 . The method of  claim 11 , further comprising:
 forming a first circuit pattern;   removing first and second dry film patterns; and   removing the first plated seed layer.   
     
     
         14 . The method of  claim 5 , wherein the forming of the second circuit layer comprises:
 forming a second plated seed layer on the second face and the via;   forming a third dry film pattern for the formation of the second circuit pattern on the second plated seed layer; and   performing electroplating to form the second circuit pattern.   
     
     
         15 . The method of  claim 14 , wherein the forming of the third dry film pattern comprises:
 forming a dry film resist on the second plated seed layer; and   exposing and developing the dry film resist.   
     
     
         16 . The method of  claim 14 , further comprising:
 removing the third dry film pattern; and   removing the second plated seed layer, after the formation of the second circuit pattern.   
     
     
         17 . A printed circuit board comprising:
 a first circuit layer provided on an insulating layer and comprising a via having an upper land and a first circuit pattern provided on a first face of the insulating layer; and   a second circuit layer provided on a second face of the insulating layer and comprising a second circuit pattern having a line width smaller than a minimum diameter of the via, and connected with the via.   
     
     
         18 . The printed circuit board of  claim 17 , wherein the via has a shape such that its diameter becomes smaller toward the second circuit pattern from the upper land.