Method for forming stair-step structures

Abstract

A method for forming a stair-step structure in a substrate is provided. An organic mask is formed over the substrate. A hardmask with a top layer and sidewall layer is formed over the organic mask. The sidewall layer of the hard mask is removed while leaving the top layer of the hardmask. The organic mask is trimmed The substrate is etched. The forming the hardmask, removing the sidewall layer, trimming the organic mask, and etching the substrate are repeated a plurality of times.

1 . A semiconductor devices with a stair-step structure formed by the method, comprising:
 a) forming an organic mask over the substrate;   b) forming a hardmask with a top layer and sidewall layer over the organic mask;   c) removing the sidewall layer of the hard mask while leaving the top layer of the hardmask;   d) trimming the organic mask;   e) etching the substrate; and   f) repeating steps a-e a plurality of times forming the stair step structure.   
     
     
         2 . The semiconductor device, as recited in  claim 1 , wherein a thickness of the top layer of the hardmask is greater than a thickness of the sidewall layer of the hardmask. 
     
     
         3 . The semiconductor device, as recited in  claim 2 , wherein the trimming the organic mask forms a roof, formed from the top layer of the hardmask, where the organic mask has been trimmed away under the roof. 
     
     
         4 . The semiconductor device, as recited in  claim 3 , wherein the thickness of the top layer is at least twice the thickness of the sidewall layer. 
     
     
         5 . The semiconductor device, as recited in  claim 4 , wherein the forming the hardmask over the organic mask provides a bias. 
     
     
         6 . The semiconductor device, as recited in  claim 5 , wherein the repeating steps a-e is repeated at least 3 times. 
     
     
         7 . The semiconductor device, as recited in  claim 6 , wherein the substrate comprises a plurality of layers, wherein each layer comprises at least two sublayers, wherein at least one of the at least two sublayers is a silicon layer. 
     
     
         8 . The semiconductor device, as recited in  claim 1 , wherein the trimming the organic mask forms a roof, formed from the top layer of the hardmask, where the organic mask has been trimmed away under the roof. 
     
     
         9 . The semiconductor device, as recited in  claim 1 , wherein the thickness of the top layer is at least twice the thickness of the sidewall layer. 
     
     
         10 . The semiconductor device, as recited in  claim 1 , wherein the forming the hardmask over the organic mask provides a bias. 
     
     
         11 . The semiconductor device, as recited in  claim 1 , wherein the repeating steps a-e is repeated at least 3 times. 
     
     
         12 . A semiconductor device with a three dimensional memory structure formed by the method, comprising:
 a) providing memory stack comprising a plurality of layers, wherein each layer comprises at least two sublayers;   b) forming an organic mask over the memory stack;   c) forming a hardmask with a top layer and sidewall layer over the organic mask;   d) removing the sidewall layer of the hard mask while leaving the top layer of the hardmask;   e) trimming the organic mask;   f) etching the memory stack, so that portions of the memory stack not covered by the organic mask are etched a depth of the thickness of a layer of the plurality of layers; and   g) repeating steps b-f a plurality of times forming the three dimensional memory structure.   
     
     
         13 . The semiconductor device, as recited in  claim 12 , wherein a thickness of the top layer of the hardmask is greater than a thickness of the sidewall layer of the hardmask. 
     
     
         14 . The semiconductor device, as recited in  claim 13 , wherein the trimming the organic mask forms a roof, formed from the top layer of the hardmask, where the organic mask has been trimmed away under the roof. 
     
     
         15 . The semiconductor device, as recited in  claim 13 , wherein steps b-f are performed in a single plasma processing chamber. 
     
     
         16 . An apparatus for etching stair-step structures in a substrate, said apparatus comprising:
 a plasma processing chamber, comprising:
 a chamber wall forming a plasma processing chamber enclosure; 
 a chuck for supporting and chucking a substrate within the plasma processing chamber enclosure; 
 a pressure regulator for regulating the pressure in the plasma processing chamber enclosure; 
 at least one electrode or coil for providing power to the plasma processing chamber enclosure for sustaining a plasma; 
 a gas inlet for providing gas into the plasma processing chamber enclosure; and 
 a gas outlet for exhausting gas from the plasma processing chamber enclosure; 
   a gas source in fluid connection with the gas inlet, comprising:
 a hardmask deposition gas source; 
 a hardmask sidewall removal gas source; 
 an organic mask trimming gas source; and 
 a substrate etching gas source; 
   a controller controllably connected to the gas source, the chuck, and the at least one electrode or coil, comprising:
 at least one processor; and 
 non-transient computer readable media, comprising:
 computer readable code for chucking a substrate with an organic mask to the chuck; 
 computer readable code for forming a hardmask with a top layer and sidewall layer over the organic mask, comprising:
 computer readable code for flowing a hardmask deposition gas from the hardmask deposition gas source into the plasma processing chamber; 
 computer readable code for forming a plasma from the hardmask deposition gas; 
 computer readable code for providing a bias voltage; and 
 computer readable code for stopping the hardmask deposition gas; 
 
 computer readable code for removing a sidewall layer of the hardmask while leaving the top layer of the hardmask, comprising:
 computer readable code for flowing a hardmask sidewall removal gas from the hardmask sidewall removal gas source into the plasma processing chamber; 
 computer readable code for forming a plasma from the hardmask sidewall removal gas; and 
 computer readable code for stopping the hardmask sidewall removal gas; 
 
 computer readable code for trimming the organic mask, comprising:
 computer readable code for flowing an organic mask trimming gas from the organic mask trimming gas source into the plasma processing chamber; 
 computer readable code for forming a plasma from the organic mask trimming gas; and 
 computer readable code for stopping the organic mask trimming gas; 
 
 computer readable code for etching the substrate, comprising:
 computer readable code for flowing a substrate etching gas from the substrate etching gas source into the plasma processing chamber; 
 computer readable code for forming a plasma from the substrate etching gas; and 
 computer readable code for stopping the substrate etching gas; and 
 
 computer readable code for repeating the forming the hardmask, removing the sidewall layer, trimming the organic mask, and etching the substrate a plurality of times. 
 
   
     
     
         17 . The apparatus, as recited in  claim 16 , wherein a thickness of the top layer of the hardmask is greater than a thickness of the sidewall layer of the hardmask. 
     
     
         18 . The apparatus, as recited in  claim 17 , wherein the computer readable code for trimming the organic mask forms a roof, formed from the top layer of the hardmask, where the organic mask has been trimmed away under the roof.