Semiconductor device

Abstract

A PN junction diode is formed by an N+ type buried layer having a proper impurity concentration and a P+ type buried layer. The P+ type buried layer is combined with a P+ type drawing layer to penetrate an N− type epitaxial layer and be connected to an anode electrode. An N+ type diffusion layer and a P+ type diffusion layer connected to and surrounding the N+ type diffusion layer are formed in the N− type epitaxial layer surrounded by the P+ type buried layer etc. The N+ type diffusion layer and the P+ type diffusion layer are connected to a cathode electrode. An ESD protection element is formed by the PN junction diode and a parasitic PNP bipolar transistor which uses the P+ type diffusion layer as the emitter, the N− type epitaxial layer as the base, and the P+ type drawing layer etc as the collector.

What is claimed is: 
     
         1 . A semiconductor device comprising:
 a semiconductor substrate of a first general conductivity type;   an epitaxial layer of a second general conductivity type formed on the semiconductor substrate;   a first buried layer of the second general conductivity type formed between the semiconductor substrate and the epitaxial layer;   a second buried layer of the first general conductivity type connected to a peripheral edge region of the first buried layer and extending from inside the semiconductor substrate into the epitaxial layer;   a drawing layer of the first general conductivity type extending from a surface portion of the epitaxial layer into the epitaxial layer so as to be connected to the second buried layer;   a first diffusion layer of the second general conductivity type extending from a surface portion of the epitaxial layer into the epitaxial layer so as to be surrounded by the second buried layer and the drawing layer in plan view of the semiconductor substrate, the first buried layer covering a bottom portion of the first diffusion layer;   a second diffusion layer of the first general conductivity type connected to and surrounding the first diffusion layer in the plan view;   a cathode electrode connected to the first diffusion layer and the second diffusion layer; and   an anode electrode connected to the drawing layer,   wherein the first buried layer and the second buried layer are configured to form a PN junction diode,   the second diffusion layer, the epitaxial layer and the drawing layer are configured to form a parasitic bipolar transistor, and   the PN junction diode and the parasitic bipolar transistor are configured to form an ESD protection element.   
     
     
         2 . The semiconductor device of  claim 1 , wherein in the parasitic bipolar transistor, the second diffusion layer operates as an emitter, the epitaxial layer operates as a base, and the drawing layer operates as a collector. 
     
     
         3 . The semiconductor device of  claim 1 , wherein the first buried layer of the PN junction diode has an impurity concentration higher than an impurity concentration of the epitaxial layer and lower than an impurity concentration of the second buried layer at least in a region adjacent to the second buried layer. 
     
     
         4 . The semiconductor device of  claim 1 , wherein the cathode electrode is connected to a power supply line and the anode electrode is connected to a ground line. 
     
     
         5 . The semiconductor device of  claim 1 , wherein the second diffusion layer and the first diffusion layer have same depths in the epitaxial layer. 
     
     
         6 . The semiconductor device of  claim 1 , wherein the second diffusion layer is extended to a same depth as a depth of the drawing layer in the epitaxial layer. 
     
     
         7 . The semiconductor device of  claim 1 , wherein an impurity concentration of the first buried layer is higher than an impurity concentration of the second buried layer except in a region of the first buried layer adjacent to the second buried layer where a breakdown voltage of the PN junction diode is determined. 
     
     
         8 . The semiconductor device of  claim 1 , wherein a plurality of ESD protection elements are formed in a grid pattern in parallel. 
     
     
         9 . A semiconductor device comprising:
 a semiconductor substrate of a first general conductivity type;   an epitaxial layer of a second general conductivity type formed on the semiconductor substrate;   a first buried layer of the second general conductivity type foamed between the semiconductor substrate and the epitaxial layer;   a second buried layer of the first general conductivity type connected to a peripheral edge region of the first buried layer and extending from inside the semiconductor substrate into the epitaxial layer;   a drawing layer of the first general conductivity type extending from a surface portion of the epitaxial layer into the epitaxial layer so as to be connected to the second buried layer;   a first diffusion layer of the second general conductivity type extending from a surface portion of the epitaxial layer into the epitaxial layer so as to be surrounded by the second buried layer and the drawing layer in plan view of the semiconductor substrate, the first buried layer covering a bottom portion of the first diffusion layer;   a second diffusion layer of the first general conductivity type connected to and surrounding the first diffusion layer in the plan view and extending deeper into the epitaxial layer than the first diffusion layer;   a cathode electrode connected to the first diffusion layer and the second diffusion layer; and   an anode electrode connected to the drawing layer,   wherein the first buried layer and the second buried layer are configured to form a PN junction diode,   the second diffusion layer, the epitaxial layer, the drawing layer and the second buried layer are configured to form a parasitic bipolar transistor, and   the PN junction diode and the parasitic bipolar transistor are configured to form an ESD protection element.   
     
     
         10 . A semiconductor device comprising:
 a semiconductor substrate of a first general conductivity type;   an epitaxial layer of a second general conductivity type formed on the semiconductor substrate;   a first buried layer of the second general conductivity type formed between the semiconductor substrate and the epitaxial layer;   a second buried layer of the first general conductivity type connected to a peripheral edge region of the first buried layer and extending from inside the semiconductor substrate into the epitaxial layer;   a drawing layer of the first general conductivity type extending from a surface portion of the epitaxial layer into the epitaxial layer so as to be connected to the second buried layer;   a first diffusion layer of the first general conductivity type extending from a surface portion of the epitaxial layer into the epitaxial layer so as to be surrounded by the second buried layer and the drawing layer in plan view of the semiconductor substrate, the first buried layer covering a bottom portion of the first diffusion layer;   a second diffusion layer of the second general conductivity type connected to and surrounding the first diffusion layer in the plan view and being shallower than the first diffusion layer in the epitaxial layer;   a cathode electrode connected to the first diffusion layer and the second diffusion layer; and   an anode electrode connected to the drawing layer,   wherein the first buried layer and the second buried layer are configure to form a PN junction diode,   the first diffusion layer, the epitaxial layer, the drawing layer and the second buried layer are configured to form a parasitic bipolar transistor, and   the PN junction diode and the parasitic bipolar transistor are configured to form an ESD protection element.